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2017 China Semiconductor Technology International Conference (CSTIC)最新文献

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Controllable shrinking of silicon oxide nanopores by high temperature annealing 氧化硅纳米孔的高温退火可控收缩
2017 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2017-03-01 DOI: 10.1109/CSTIC.2017.7919879
Jian Chen, T. Deng, Zewen Liu, Haizhi Songc
{"title":"Controllable shrinking of silicon oxide nanopores by high temperature annealing","authors":"Jian Chen, T. Deng, Zewen Liu, Haizhi Songc","doi":"10.1109/CSTIC.2017.7919879","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919879","url":null,"abstract":"This paper presents a novel method for fabricating silicon oxide nanopores. First, pores of 80–400 nm were fabricated in a free-standing silicon membrane by anisotropic wet etching process. After thermal oxidation of 90 nm silicon oxide, the pores can be reduced to 35–300 nm. Finally, high temperature annealing promotes the viscous flow of the silicon dioxide membrane and results in shrinking the pores to sub-15 nm, with an estimated precision of 1 nm. Our results are in agreement with the surface-tension-driven model.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"49 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76401950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Depletion-mode MOS capacitor modeling investigation 耗尽模式MOS电容建模研究
2017 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2017-03-01 DOI: 10.1109/CSTIC.2017.7919748
C. Tseng, Yuan Sheng Wang
{"title":"Depletion-mode MOS capacitor modeling investigation","authors":"C. Tseng, Yuan Sheng Wang","doi":"10.1109/CSTIC.2017.7919748","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919748","url":null,"abstract":"A depletion-mode MOS (DMOS) capacitor modeling methodology with high accuracy and feasibility is proposed. Currently, it is lack of compact model relevant DMOS capacitor modeling but it is significant importance in A/D converters (ADCs) for CMOS image sensor circuit. This modeling methodology not only could provide good accuracy on geometry scaling but also with voltage and temperature sensitivity.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"44 9 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76513915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Effective method to automatically measure the profile parameters of integrated circuit from SEM/TEM/STEM images 从SEM/TEM/STEM图像中自动测量集成电路轮廓参数的有效方法
2017 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2017-03-01 DOI: 10.1109/CSTIC.2017.7919843
Xiaolin Zhang, Zubiao Fu, Yi Huang, Alien Lin, Yaoming Shi, Yiping Xu
{"title":"Effective method to automatically measure the profile parameters of integrated circuit from SEM/TEM/STEM images","authors":"Xiaolin Zhang, Zubiao Fu, Yi Huang, Alien Lin, Yaoming Shi, Yiping Xu","doi":"10.1109/CSTIC.2017.7919843","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919843","url":null,"abstract":"An effective image based method to automatically measure the profile parameters (PPs), including the critical dimensions (CDs), the full height and other structural parameters, of the integrated circuit (IC) devices in batch is proposed. In this method, templates are used to indicate the patterns of interest and the regions of the desired PPs; pattern recognition and PPs analysis algorithms are applied to determine the exact PPs from the underdetermined IC device images. In practice, the proposed method was proven of higher efficiency, more accuracy and better repeatability than the traditional manual measurement.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"11 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78297383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Sputter deposition technology for Al(1−x)ScxN films with high Sc concentration 高Sc浓度Al(1−x)ScxN薄膜的溅射沉积技术
2017 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2017-03-01 DOI: 10.1109/CSTIC.2017.7919885
B. Heinz, S. Mertin, O. Rattunde, M. Dubois, S. Nicolay, G. Christmann, Maurus Tschirky, P. Muralt
{"title":"Sputter deposition technology for Al(1−x)ScxN films with high Sc concentration","authors":"B. Heinz, S. Mertin, O. Rattunde, M. Dubois, S. Nicolay, G. Christmann, Maurus Tschirky, P. Muralt","doi":"10.1109/CSTIC.2017.7919885","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919885","url":null,"abstract":"Aluminium scandium nitride (Al1−xScxN) with its strongly enhanced piezoelectric response is the upcoming piezoelectric material of choice in next generation RF filters, sensors, actuators and energy harvesting devices. This paper will concentrate on the deposition technology for Al1−xScxN films with high Sc content. Films with Sc concentrations close to 43 at% have been grown on 200-mm substrates using a cluster type sputter deposition tool. The piezoelectric response will be discussed and correlated with the deposition parameters and film structural properties. The steps required to deliver a high-volume production solution for high Sc concentration will be described.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"53 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90667175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A study of n-induced residue defect on gate oxide after lithography rework 光刻返工后栅氧化层n诱导残馀缺陷的研究
2017 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2017-03-01 DOI: 10.1109/CSTIC.2017.7919760
Z. Fang, Chang Liu, Zhoujun Pan
{"title":"A study of n-induced residue defect on gate oxide after lithography rework","authors":"Z. Fang, Chang Liu, Zhoujun Pan","doi":"10.1109/CSTIC.2017.7919760","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919760","url":null,"abstract":"In order to improve the semiconductor device performance, decoupled plasma nitridation (DPN) process was used to form the ultra-thin gate oxide film. But we recently found serious residue defect on gate oxide film if we did lithography rework with chemical method. This defect was like a circular-pattern about several-micron in diameter and hard to be removed. The results also showed that the thickness decrease and photoresist (PR) footing phenomenon would become worse after rework. After performing some experiments, we found that the N element doped in the gate oxide film could be one possible origin for this defect. And a model was proposed to explain the generation mechanism of this residue defect based on above analysis. Finally, an optimized lithography rework method was used to avoid the generation of the defect successfully.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"247 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80627059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A novel OLED-on-silicon microdisplay drive circuit with the digital analog hybrid scan strategy 一种新型的基于数模混合扫描策略的硅基oled微显示驱动电路
2017 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2017-03-01 DOI: 10.1109/CSTIC.2017.7919891
Yong-Juan Chu, Ting-zhou Mu, Yuan Ji, Yunsen Yu, F. Ran, Jiao Li
{"title":"A novel OLED-on-silicon microdisplay drive circuit with the digital analog hybrid scan strategy","authors":"Yong-Juan Chu, Ting-zhou Mu, Yuan Ji, Yunsen Yu, F. Ran, Jiao Li","doi":"10.1109/CSTIC.2017.7919891","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919891","url":null,"abstract":"A novel AMOLED-on-silicon microdisplay driver circuit with the digital-analog-hybrid scan strategy is designed for high resolution and high frame refresh rate display. The strategy of the digital-analog-hybrid scan is analyzed. A particularly designed multiplex column driver circuit is proposed. The column driver circuit is simulated. The experimental results show that the digital-analog-hybrid scan method can effectively reduce data flow.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"194 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76053471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Defects and lifetime prediction for GE pMOSFETs under AC NBTI stresses 交流NBTI应力下GE pmosfet的缺陷及寿命预测
2017 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2017-03-01 DOI: 10.1109/CSTIC.2017.7919733
J. Zhang, Jigang Ma, W. Zhang, Z. Ji
{"title":"Defects and lifetime prediction for GE pMOSFETs under AC NBTI stresses","authors":"J. Zhang, Jigang Ma, W. Zhang, Z. Ji","doi":"10.1109/CSTIC.2017.7919733","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919733","url":null,"abstract":"Germanium has higher hole mobility and is a candidate for replacing silicon for pMOSFETs. This work reviews the recent progresses in understanding the negative bias temperature instability (NBTI) of Ge pMOSFETs and compares it with SiON/Si devices. Both Ge and SiON/Si devices have two groups of defects: as-grown hole traps (AHT) and generated defects (GDs). The generation process, however, is different: GDs are interface-controlled for SiON/Si and dielectric-controlled for Ge devices. This leads to substantially higher GDs under DC stress than under AC stress for Ge, although they are similar for SiON/Si devices. Moreover, GDs alter their energy levels with charge status and can be reset to original precursor states after neutralization for Ge, but these processes are insignificant for SiON/Si. The impact of these differences on lifetime prediction will be presented and the defects and physical mechanism will be explored.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"135 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73843362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Study of poly etch for performance improvement with alternative spin-on materials in FinFET technology node 在FinFET技术节点上，采用可选自旋材料改进多晶蚀刻技术的研究
2017 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2017-03-01 DOI: 10.1109/CSTIC.2017.7919788
Yan Wang, Qiu-hua Han, H. Zhang
{"title":"Study of poly etch for performance improvement with alternative spin-on materials in FinFET technology node","authors":"Yan Wang, Qiu-hua Han, H. Zhang","doi":"10.1109/CSTIC.2017.7919788","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919788","url":null,"abstract":"In this paper, we systematically investigate the poly etch performance with three different kinds of spin-on materials (BL organic coating material, and two other spin-on materials A and B) in P2 cut process from the point view of defect and process control. Our results show that with one kind of new spin-on material B, the bubble defect performance can be significantly improved. With different gas ratio control, we can achieve comparable etch rate selectivity of B to the hard mask. Thus, the P2 cut process can be well controlled. Finally, we delivered one process with B coating material.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"18 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77317206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Novel leveling materials for copper deposition in advanced packaging 先进封装中沉积铜的新型流平材料
2017 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2017-03-01 DOI: 10.1109/CSTIC.2017.7919857
T. Ma, Jiang Wang, Zifang Zhu, Peipei Dong
{"title":"Novel leveling materials for copper deposition in advanced packaging","authors":"T. Ma, Jiang Wang, Zifang Zhu, Peipei Dong","doi":"10.1109/CSTIC.2017.7919857","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919857","url":null,"abstract":"Electroplated copper is rapidly becoming the core technology in wafer level packaging. Although copper pillar technology is not new to the semiconductor industry, it is not without significant challenges. One of the most challenges is to obtain desired co-planarity and bump shape under high throughput and various design. Meanwhile, material properties began to gain people's attention. This paper addresses the challenges with a novel class of copper plating leveling composition, L118 system, which has shown remarkable electrochemical modulation abilities on different patterns. XRD (X-ray diffraction spectra) and FIB (focused ion beam) are utilized to investigate the microstructure of the copper pillars, which exhibits that deposited copper with the novel additives is preferentially (111) textured.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"37 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77116635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Development of plating resist for FO-WLP FO-WLP电镀抗蚀剂的研制
2017 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2017-03-01 DOI: 10.1109/CSTIC.2017.7919859
K. Okamoto
{"title":"Development of plating resist for FO-WLP","authors":"K. Okamoto","doi":"10.1109/CSTIC.2017.7919859","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919859","url":null,"abstract":"We report on the latest ultra-thick photo resist to fabricate high copper pillars over 100um for FO-WLP. The new resist shows excellent coating performance to achieve 100um thickness in a single coat, or over 200um thickness with double coating, on 12 inch wafer. The resist provides good coating uniformity without bubbles, defects, wrinkles or other errors. On top of that, the new material design enables finer resolution for ultra-thick films, with an aspect ratio of 4 and beyond. We also report high copper pillars fabricated with the new THB resist. It is expected that the new ultra-thick resist will be the best candidate for FO-WLP. We will discuss the new material concept in more detail.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"23 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80598394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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