2017 China Semiconductor Technology International Conference (CSTIC)最新文献_第6页

A low noise SPAD pixel array with analog readout method 具有模拟读出方法的低噪声SPAD像素阵列

2017 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2017-03-01 DOI: 10.1109/CSTIC.2017.7919888

RuiMing Luo, Yue Xu, Bin Li

引用次数: 0

Optimization of slurry and process parameter on chemical mechanical polishing of CR-doped Sb2Te3 thin film 掺铬Sb2Te3薄膜化学机械抛光浆料及工艺参数优化

2017 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2017-03-01 DOI: 10.1109/CSTIC.2017.7919819

Ruifang Huo, F. Wang, Yulin Feng, Yemei Han, Yujie Yuan, Kailiang Zhang

引用次数: 1

High efficiency test system for envelope tracking Power amplifier 功率放大器包络跟踪高效测试系统

2017 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2017-03-01 DOI: 10.1109/CSTIC.2017.7919847

Feifan Du, Hui Yu

引用次数: 2

High-bandwidth IC interconnects with silicon interposers and bridges for 3D multi-chip integration and packaging 高带宽集成电路互连与硅中间体和桥，用于3D多芯片集成和封装

2017 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2017-03-01 DOI: 10.1109/CSTIC.2017.7919874

B. Wu

引用次数: 6

Passivation quality and electrical characteristics for boron doped hydrogenated amorphous silicon film 掺硼氢化非晶硅膜的钝化质量和电学特性

2017 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2017-03-01 DOI: 10.1109/CSTIC.2017.7919798

Ching-Lin Tseng, Y. Hsieh, Chien-Chieh Lee, Hsiang-Chih Yu, Tomi T. T. Li

{"title":"Passivation quality and electrical characteristics for boron doped hydrogenated amorphous silicon film","authors":"Ching-Lin Tseng, Y. Hsieh, Chien-Chieh Lee, Hsiang-Chih Yu, Tomi T. T. Li","doi":"10.1109/CSTIC.2017.7919798","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919798","url":null,"abstract":"Borons doped amorphous silicon (a-Si:H) that deposited on a n-type silicon substrate was prepared by plasma enhanced chemical vapor deposition (PECVD). The conductivity increases with increasing B2H6 flow when the electrode distance, working pressure and total flow rate are fixed. The Ellipsometer, Four Point Sheet Resistance Meter, Hall measurement, Secondary Ion Mass Spectrometer and Photo-conductance lifetime tester were used to obtain the electrical and physical properties of thin films. The research shows that while changing process parameters, the effect on the film that has the good conductivity and the carrier lifetime are most critical. When the amounts of the boron atoms increase, the conducting properties of the boron-doped hydrogenated amorphous silicon film increase effectively. However, too much boron atoms increase densities of the defects, thus reduce the carrier lifetime and affect the activation of boron atoms in films. Based on the results of the carrier lifetime ratio on intrinsic layer and stacked dopant layer, it is found that the carrier lifetime of the doping layer stacks over intrinsic layer can effectively improve the field effect on passivation film quality.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"13 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84091925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

The incorporation of the pattern matching approach into a post-OPC repair flow 将模式匹配方法纳入opc后修复流程

2017 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2017-03-01 DOI: 10.1109/CSTIC.2017.7919775

Y. Du

{"title":"The incorporation of the pattern matching approach into a post-OPC repair flow","authors":"Y. Du","doi":"10.1109/CSTIC.2017.7919775","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919775","url":null,"abstract":"The model based optical proximity correction (OPC) systematically computes the mask compensation that will be applied to the main features of circuits with sub-wavelength sizes. Even a sophisticated OPC recipe could render thousands of weak points, below the specs. An automatic repair flow may correct most of these post-OPC weak points. The remaining errors will have to demand engineers' visual inspections and subsequent manual fixings; and it might cost a considerable amount of human efforts and hence compromise the turnaround time (TAT). After performing several tape-outs, we have also noticed some weak points that need to be fixed afterward share certain commonalities. This inspires us to incorporate the pattern matching (PM) approach into our post-OPC repair flow. For the previous tape-outs, the remaining weak points will be fixed manually or be fixed by a special OPC recipe. Thus our old knowledge can directly provide proper OPC solutions for these known weak points. For a new tape-out, the design patterns associated with these weak points scan the post-OPC layer and find the match. Then, the proper OPC solutions will be pasted to these matched locations to complete repair process, allowing us to avoid repeatedly performing the manual fixings for the same types of weak points. This approach will also help identify certain OPC weak points that are proven to be fine by the wafer data. This type of weak points can be automatically waived by the OPCV verification. The incorporation of the PM approach into our repair flow can significantly reduce the TAT for a new tape-out.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"20 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88315114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Illumination optimization for lithography tools ope matching at 28 nm nodes 光刻工具的照明优化实现了28nm节点的匹配

2017 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2017-03-01 DOI: 10.1109/CSTIC.2017.7919767

Wuping Wang, Long Qin, Zhengkai Yang, Yulong Li, Zhibiao Mao, Yu Zhang

引用次数: 1

Application of OPE Master for critical layer OPE matching OPE Master在关键层OPE匹配中的应用

2017 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2017-03-01 DOI: 10.1109/CSTIC.2017.7919756

Yuan Tao, Yifei Liu, Yuanzhao Ma, Zhenyu Yang, Chun Shao, Xuedong Fan, J. Ikeda, K. Fujii

引用次数: 1

Metal-electrode-dependent negative photoconductance response of the nanoscale conducting filament in the SiO2-metal stack 二氧化硅-金属叠层中纳米级导电灯丝的金属电极负光导响应

2017 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2017-03-01 DOI: 10.1109/CSTIC.2017.7919745

T. Kawashima, Y. Zhou, K. S. Yew, H. Z. Zhang, D. Ang

引用次数: 0

Ultrapure chemical components for next generation materials 用于新一代材料的超纯化学成分

2017 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2017-03-01 DOI: 10.1109/CSTIC.2017.7919765

Hyun Yong Cho, Rameshwaram Sharma, Jeffrey D. Fogle

引用次数: 0