14nm金属栅极薄膜堆的发展与挑战

Jianhua Xu, Anni Wang, Jun He, X. Jing, Ziying Zhang, Beichao Zhang
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引用次数: 3

摘要

随着集成电路技术向16/ 14nm及更先进的方向发展,具有优异漏失性能的FinFET架构成为集成电路行业的主流。然而,由于其非常激进的结构和外形,CD收缩,阴影效应和空白填充困难,也给集成和工艺带来了很大的挑战。本文研究了原子层沉积(ALD)金属薄膜,包括TaN, TiN (TiSiN), TiAl和CVD W,用于替代金属栅极的应用。将讨论和解决台阶覆盖和间隙填充,加载效果和工作功能可调范围的挑战。高K封盖层(TiN或TaN)、功功能金属(TiN & TiAl)、W势垒层(TiN)的厚度对N/P MOS器件Vt均有较强的影响,且功功能可调范围在300 mv以上。此外,高Al: Ti比工艺、TiAl与W势垒TiN之间的界面特殊处理以及不同W工艺均可降低NMOS Vt。最后,ALD和CVD工艺在CD开口大于5nm时(宽高比约为20∶1)具有良好的补隙性能。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
14nm metal gate film stack development and challenges
As IC technology advances to 16/14 nm and beyond, FinFET architecture with advantage of excellent leakage performance becomes main stream in IC industry. However, it also brings big challenges for integration and processes due to its very aggressive structure and profile, CD shrinkage, shadow effect and gap-fill difficulty. In this work, atomic layer deposition (ALD) metal films, including TaN, TiN (TiSiN), TiAl and CVD W, were studied for replacement metal gate application. Challenges of step coverage & gap-fill, loading effect and tunable range of work function will be discussed and addressed. Thickness of high K capping layer (TiN or TaN), work function metal (TiN & TiAl), W barrier layer (TiN) all show strong effect on N/P MOS device Vt, and more than 300 mv tunable range of work function can be achieved. Besides, higher Al : Ti ratio process, interfacial special treatment between TiAl & W barrier TiN and different W process can lower down NMOS Vt. At the last, ALD and CVD process ensure good gap-fill performance when CD opening is larger than 5nm (aspect ratio is about 20∶1).
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