{"title":"A low noise SPAD pixel array with analog readout method","authors":"RuiMing Luo, Yue Xu, Bin Li","doi":"10.1109/CSTIC.2017.7919888","DOIUrl":null,"url":null,"abstract":"This paper presents a parallel readout circuit for high density single photon avalanche diode (SPAD) pixel array. Each pixel consists of analog quenching circuit and counting circuit. Column parallel readout method is adopted and every eight columns of array pixel shares one multiplexer where the analog output signals of these pixels are selected to pass it subsequently. After that, the signals will be sent to correlated double sampling (CDS) circuit for elimination of fixed pattern noise (FPN). Then the processed signals will be inputted to off-chip high speed ADC for analog to digital conversion. The shared CDS can reduce chip area without lowering performance.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"78 1","pages":"1-3"},"PeriodicalIF":0.0000,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 China Semiconductor Technology International Conference (CSTIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CSTIC.2017.7919888","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper presents a parallel readout circuit for high density single photon avalanche diode (SPAD) pixel array. Each pixel consists of analog quenching circuit and counting circuit. Column parallel readout method is adopted and every eight columns of array pixel shares one multiplexer where the analog output signals of these pixels are selected to pass it subsequently. After that, the signals will be sent to correlated double sampling (CDS) circuit for elimination of fixed pattern noise (FPN). Then the processed signals will be inputted to off-chip high speed ADC for analog to digital conversion. The shared CDS can reduce chip area without lowering performance.