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Passivation quality and electrical characteristics for boron doped hydrogenated amorphous silicon film 掺硼氢化非晶硅膜的钝化质量和电学特性
2017 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2017-03-01 DOI: 10.1109/CSTIC.2017.7919798
Ching-Lin Tseng, Y. Hsieh, Chien-Chieh Lee, Hsiang-Chih Yu, Tomi T. T. Li
{"title":"Passivation quality and electrical characteristics for boron doped hydrogenated amorphous silicon film","authors":"Ching-Lin Tseng, Y. Hsieh, Chien-Chieh Lee, Hsiang-Chih Yu, Tomi T. T. Li","doi":"10.1109/CSTIC.2017.7919798","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919798","url":null,"abstract":"Borons doped amorphous silicon (a-Si:H) that deposited on a n-type silicon substrate was prepared by plasma enhanced chemical vapor deposition (PECVD). The conductivity increases with increasing B2H6 flow when the electrode distance, working pressure and total flow rate are fixed. The Ellipsometer, Four Point Sheet Resistance Meter, Hall measurement, Secondary Ion Mass Spectrometer and Photo-conductance lifetime tester were used to obtain the electrical and physical properties of thin films. The research shows that while changing process parameters, the effect on the film that has the good conductivity and the carrier lifetime are most critical. When the amounts of the boron atoms increase, the conducting properties of the boron-doped hydrogenated amorphous silicon film increase effectively. However, too much boron atoms increase densities of the defects, thus reduce the carrier lifetime and affect the activation of boron atoms in films. Based on the results of the carrier lifetime ratio on intrinsic layer and stacked dopant layer, it is found that the carrier lifetime of the doping layer stacks over intrinsic layer can effectively improve the field effect on passivation film quality.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"13 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84091925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Metal-electrode-dependent negative photoconductance response of the nanoscale conducting filament in the SiO2-metal stack 二氧化硅-金属叠层中纳米级导电灯丝的金属电极负光导响应
2017 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2017-03-01 DOI: 10.1109/CSTIC.2017.7919745
T. Kawashima, Y. Zhou, K. S. Yew, H. Z. Zhang, D. Ang
{"title":"Metal-electrode-dependent negative photoconductance response of the nanoscale conducting filament in the SiO2-metal stack","authors":"T. Kawashima, Y. Zhou, K. S. Yew, H. Z. Zhang, D. Ang","doi":"10.1109/CSTIC.2017.7919745","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919745","url":null,"abstract":"Nanoscale resistance reset of the SiO2/M stack (where M=Cu, Ni, Ti, Al, p-type Si) was investigated via a conductive atomic force microscope (C-AFM). Visible-light illumination triggers a resistance reset for Ti, Al and p-type Si electrodes, however such a behavior is not always observed for the Cu and Ni electrodes. Conversely, electrical reset is possible for Cu and Ni, but not for the others. The observed variations in optical and electrical induced resistive switching behaviors may be caused by a metal-electrode-dependent conducting filament.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"6 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81903411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Ultrapure chemical components for next generation materials 用于新一代材料的超纯化学成分
2017 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2017-03-01 DOI: 10.1109/CSTIC.2017.7919765
Hyun Yong Cho, Rameshwaram Sharma, Jeffrey D. Fogle
{"title":"Ultrapure chemical components for next generation materials","authors":"Hyun Yong Cho, Rameshwaram Sharma, Jeffrey D. Fogle","doi":"10.1109/CSTIC.2017.7919765","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919765","url":null,"abstract":"Ultrapure chemical components for next generation materials for semiconductor manufacture are required due to chip yield enhancement. Some components for photoresist, cross linker, monomer, and photo acid generator (PAG) can be provided as representative ultrapure chemical components which have below 10 ppb level ionic metal impurities by particular purification methods.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"20 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78758508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Application of OPE Master for critical layer OPE matching OPE Master在关键层OPE匹配中的应用
2017 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2017-03-01 DOI: 10.1109/CSTIC.2017.7919756
Yuan Tao, Yifei Liu, Yuanzhao Ma, Zhenyu Yang, Chun Shao, Xuedong Fan, J. Ikeda, K. Fujii
{"title":"Application of OPE Master for critical layer OPE matching","authors":"Yuan Tao, Yifei Liu, Yuanzhao Ma, Zhenyu Yang, Chun Shao, Xuedong Fan, J. Ikeda, K. Fujii","doi":"10.1109/CSTIC.2017.7919756","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919756","url":null,"abstract":"Tool-to-tool matching of optical proximity effect (OPE) properties is required and the procedure is called OPE matching. Nikon has developed a software called OPE Master for the purpose, which can decrease OPE errors with emphasis placed on critical dimension (CD) errors by optimizing exposure tool's parameters, such as lens numerical aperture (LNA), pupilgram intensity distribution, pupilgram distortion. Thanks to its high affinity to the Nikon NSR series scanners, the software ensures higher accuracies and short turn-around-time (TAT) as it can directly communicate with exposure tools. One secondary benefit of such bilateral communication is that it can realize high data security as we have no need to send data used during OPE matching to the outside of the fab. In this paper, we are going to introduce OPE Master and report one successful use case. which is a critical layer in 55nm node in which OPE errors has been improved by about 33% which is well within the goal of the process requirements.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"10 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90437988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Illumination optimization for lithography tools ope matching at 28 nm nodes 光刻工具的照明优化实现了28nm节点的匹配
2017 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2017-03-01 DOI: 10.1109/CSTIC.2017.7919767
Wuping Wang, Long Qin, Zhengkai Yang, Yulong Li, Zhibiao Mao, Yu Zhang
{"title":"Illumination optimization for lithography tools ope matching at 28 nm nodes","authors":"Wuping Wang, Long Qin, Zhengkai Yang, Yulong Li, Zhibiao Mao, Yu Zhang","doi":"10.1109/CSTIC.2017.7919767","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919767","url":null,"abstract":"The CD (critical dimension) of large scale integrated circuit was dominated by lithography process. The 193 nm immersion lithography nowadays has been widely used in chip manufacturing at 28 nm nodes. With the application of Nikon 193 nm immersion lithography tools, it is significant to match the Nikon immersion with ASML through OPE (Optical Proximity Effect). Good scanner matching will be beneficial for extending Nikon 193 nm immersion lithography tools and effectively improving production efficiency. In this paper, based on the OPE research between Nikon immersion tool and ASML immersion tool, we have developed a set of matching method for both immersion tools at 28 nm node and realized the 28 nm lithography process transfer from ASML immersion tool to Nikon immersion tool.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"77 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86873093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Effects of copper line-edge roughness on TDDB at advanced technology nodes of 28NM and beyond 铜线边缘粗糙度对28NM及以上先进工艺节点TDDB的影响
2017 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2017-03-01 DOI: 10.1109/CSTIC.2017.7919832
Dongyan Tao, Jinling Xu, Yanhui Sun, W. Chien, JS Chen, Guan Zhang
{"title":"Effects of copper line-edge roughness on TDDB at advanced technology nodes of 28NM and beyond","authors":"Dongyan Tao, Jinling Xu, Yanhui Sun, W. Chien, JS Chen, Guan Zhang","doi":"10.1109/CSTIC.2017.7919832","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919832","url":null,"abstract":"Ultra low-k films are used in advanced technologies as dielectric interlayers in Cu interconnects. Due to its high porosity, manufacturing reliable low-k films faces many challenges. This paper discusses the reliability of time dependent dielectric breakdown (TDDB). Degradation of the TDDB lifetime can be observed when there is an abnormal I–V breakdown. Our study characterized the interaction of the breakdown leakage to the etch profile. It has shown that the etch profile weak points have impacts on the TDDB lifetime. By characterizing the Cu etching profile and establishing inline correlations to its TDDB lifetime, a new evaluation method was identified to quickly and precisely reflect the TDDB lifetime performance.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"29 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88856034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A reliability study of a new embedded flash to reduce charge-loss issue 一种降低电荷损耗的新型嵌入式闪存的可靠性研究
2017 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2017-03-01 DOI: 10.1109/CSTIC.2017.7919738
Lingling Shao, Y. Zhao, Wei Han, W. Chien
{"title":"A reliability study of a new embedded flash to reduce charge-loss issue","authors":"Lingling Shao, Y. Zhao, Wei Han, W. Chien","doi":"10.1109/CSTIC.2017.7919738","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919738","url":null,"abstract":"We investigated the mechanism of read stress and standby with power-on after more than 20 program/erase cycles, which cause conventional embedded flash memory read “0” fail. To solve this, a new e-flash with reversed drain-source cell device was introduced. In this paper, we studied the reliability performance of conventional and the new e-flash. Experimental results proved that the newly designed e-flash exhibits superior performance in terms of data retention, endurance, and the potential at multilevel operations.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"23 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87522673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Electrostatic discharge failure control of IC package by epoxy molding compound modification 环氧成型复合改性IC封装静电放电失效控制
2017 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2017-03-01 DOI: 10.1109/CSTIC.2017.7919875
Byung-Seon Kong, Sang-Sun Lee, D. Lee, H. Choi, Hyun Woo Kim
{"title":"Electrostatic discharge failure control of IC package by epoxy molding compound modification","authors":"Byung-Seon Kong, Sang-Sun Lee, D. Lee, H. Choi, Hyun Woo Kim","doi":"10.1109/CSTIC.2017.7919875","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919875","url":null,"abstract":"By changing curing accelerator and modifying the volume resistivity of epoxy molding compound (EMC), electrostatic characteristics of EMC applied package can be improved and electrostatic damage of IC device was reduced. EMC with phosphonium salt accelerator results in much lower ESD failure than EMC with phosphine salt accelerator. Because the volume resistivity of phosphonium salt applied EMC is lower than that of phosphine salt, it could easily dissipate the static electricity that generated inside of package during or after transfer molding process.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"36 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88230168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design and implementation of a high quality R-peak detection algorithm 一种高质量r峰检测算法的设计与实现
2017 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2017-03-01 DOI: 10.1109/CSTIC.2017.7919897
Zhongmin Lin, Bo Wang, Hao Chen, Ying Zhang, Xin-an Wang
{"title":"Design and implementation of a high quality R-peak detection algorithm","authors":"Zhongmin Lin, Bo Wang, Hao Chen, Ying Zhang, Xin-an Wang","doi":"10.1109/CSTIC.2017.7919897","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919897","url":null,"abstract":"In modern medicine, electrocardiogram (ECG) is an important way to diagnose cardiovascular disease and monitor health information. The detection of R-peak is very important in ECG signal processing. To improve the accuracy and sensitivity of detection, a compound algorithm with high quality is presented in this paper. The algorithm removes high frequency noise and power frequency noise through an IIR low-pass filter, then do wavelet transform to the filtered signal. Adaptive threshold was used to extract modulus maxima. Rechecking is applied when there are mistakes. Additionally, template matching method is exploited in the rechecking to false detection. The algorithm is evaluated by using MIT-BIH arrhythmia database [1]. Finally, we obtained sensitivity of 99.79% and accuracy of 99.81%.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"14 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84828062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Challenges in Chemical Mechanical Planarization defects of 7nm device and its improvement opportunities 7nm器件化学机械平面化缺陷的挑战及改进机会
2017 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2017-03-01 DOI: 10.1109/CSTIC.2017.7919815
Ji Chul Yang, Dinesh K. Penigalapati, T. Chao, W. Lu, D. Koli
{"title":"Challenges in Chemical Mechanical Planarization defects of 7nm device and its improvement opportunities","authors":"Ji Chul Yang, Dinesh K. Penigalapati, T. Chao, W. Lu, D. Koli","doi":"10.1109/CSTIC.2017.7919815","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919815","url":null,"abstract":"CMP (Chemical Mechanical Planarization) defects are always one of the top yield detractors in IC (Integrated Circuit) devices since CMP processes have been applied in the semiconductor industry. Most of all, new structures and materials in 7nm devices make it challenging for CMP processes to meet device requirements. The CMP process obviously needs to control or contain not only the number of defects but also defect size in accordance with scaling speed. In this paper, the results of fundamental studies to elucidate CMP defects will be introduced and discussed as they pertain to 7nm devices. This paper will cover the phenomena and its research activities about atomic scale scratches, dishing control in uneven surface topography and surface defects with 7 nm logic device.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"69 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83879564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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