A concise and precise model of the gate delay for EDA simulation

This paper considers the relationship between the static gate delay and the supply voltage of the digital integrated circuit. An empirical equation with physical implication is proposed for calculating the static gate delay. The expression of the gate delay is very simple. It contains only three constants. The calculation includes only one subtraction step, one division step and one addition step. Transistor level simulations are performed to verify the equation. The model matches the experiment results precisely. It is valid for various technologies, gate types, and operation temperatures. The equation can be applied in EDA tools to simulate the timing of the circuit under the PVT variation and the electromagnetic interference.