2012 IEEE Silicon Nanoelectronics Workshop (SNW)最新文献

{"title":"Effect of Cu insertion layer between top electrode and switching layer on resistive switching characteristics","authors":"Sunghun Jung, Jeong-Hoon Oh, K. Ryoo, Sungjun Kim, Jong-Ho Lee, Hyungcheol Shin, Byung-Gook Park","doi":"10.1109/SNW.2012.6243355","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243355","url":null,"abstract":"By inserting copper (Cu) metal layer between platinum (Pt) and titanium dioxide (TiO2), we have observed both unipolar and bipolar resistive switching characteristics in Pt/Cu/TiO2/Pt stacked RRAM cell. In order to analyze the conduction mechanism, we have conducted I-V fitting. And based on measurement results of bias polarity dependency, we have found that copper plays a role as oxygen reservoir. It can explain redox mechanism in bipolar resistive switching cell.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77360166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Low standby power charge trap flash memory with tunneling field effect transistor","authors":"M. Han, Jong Ho Lee, D. Seo, Chong-Dae Park, Youngcheol Oh, I. Cho","doi":"10.1109/SNW.2012.6243349","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243349","url":null,"abstract":"SONOS memory with TFET is proposed to achieve off leakage current characteristics. SONOS memory with TFET exhibits extremely small off state leakage current, good FN program efficiency. Program characteristics and disturbance characteristics were investigated with device simulation. It is expected that SONOS memory with TFET can be a promising candidate for mobile devices with require low-power consumption.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73406586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Graphene fillers for ultra-efficient thermal interface materials","authors":"K. Shahil, V. Goyal, R. Gulotty, A. Balandin","doi":"10.1109/SNW.2012.6243284","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243284","url":null,"abstract":"Summary form only given. Continuous scaling of Si CMOS devices and circuits, increased speed and integration densities resulted in problems with thermal management of nanoscale device and computer chips. Further progress in information, communication and energy storage technologies requires more efficient heat removal methods and stimulates the search for thermal interface material (TIMs) with enhanced thermal conductivity. The commonly used TIMs are filled with the particles such as silver or silica. The conventional TIMs require high volume fractions of the filler (~70%) to achieve thermal conductivity of ~1-5 W/mK. Recently, some of us discovered that graphene has extremely high intrinsic thermal conductivity, which exceeds that of carbon nanotubes. To use this property for thermal management of nanoscale electronic devices, we utilized the inexpensive liquid-phase exfoliated graphene and multi-layer graphene (MLG) as filler materials in TIMs. The thermal properties of the obtained graphene-epoxy composites were measured using the “laser flash” technique. It was found that the thermal conductivity enhancement factor exceeded a factor of 23 at 10% of the graphene volume loading fraction. This enhancement is larger than anything that has been achieved using other fillers. We have also tested graphene flakes in the electrically-conductive hybrid graphene-metal particle TIMs. The thermal conductivity of resulting composites was increased by a factor of ~5 in a temperature range from 300 K to 400 K at a small graphene loading fraction of 5-vol.-%. The unusually strong enhancement of thermal properties was attributed to the high thermal conductivity of graphene, strong graphene coupling to matrix materials and the large range of the length-scale - from nanometers to micrometers - of the graphene and silver particle fillers. Graphene-based TIMs have a number of other advantages related to their viscosity and adhesion, which meet the industry requirements. Our results suggest that graphene can become excellent filler materials in the next generation of TIMs for the electronic, optoelectronic and photovoltaic solar cell applications.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73151364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The impact of the carrier transport on the random dopant induced drain current variation in the saturation regime of advanced strained-silicon CMOS devices","authors":"E. Hsieh, S. Chung, C. Tsai, R. Huang, C. Tsai, C. Liang","doi":"10.1109/SNW.2012.6243345","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243345","url":null,"abstract":"The variation of saturation drain current (I_d,sat), induced by the random dopant variation (RDF), has been extensively studied by a new multivariate analysis method. It was found that the variation of I_d,sat is originated from V_th,sat and saturation velocity (V_sat), while the variation of V_th,sat comes from the drain induced barrier lowering (DIBL). However, the experimental results shows that V_sat dominates the variation of I_d,sat. From the transport theory, V_sat is further decomposed into V_inj and B_sat, showing that V_inj is the dominant factor of I_d,sat variation. The faster the V_inj is, the less the I_d,sat variation becomes. If one improves the injection velocity, then the variation of I_d,sat can be suppressed. This has been one of the significant benefits of strained silicon technology in CMOS device scaling.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79745294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Mapping of single donors in nano-scale MOSFETs at low temperature","authors":"J. Verduijn, G. Tettamanzi, R. Wacquez, B. Roche, B. Voisin, X. Jehl, M. Sanquer, S. Rogge","doi":"10.1109/SNW.2012.6243341","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243341","url":null,"abstract":"Using low temperature measurements we have been able to identify the influence of only about five donors in the channel the channel of an ultra-scaled MOSFET as the source of an anomalously low room temperature threshold voltage and large sub-threshold slope. Further we observe the influence of these dopants on the low temperature threshold voltage shift as a function of applied back gate voltage. The understanding of this behavior allows us to identify resonant tunneling mediated by a single donor in the channel of a doped channel device and we show that the back gate strongly modifies the tunnel coupling. These results give new insights in dopant transport in ultra-scaled MOSFETs, which is relevant for conventional device characteristics as well as for new dopant-based device architectures.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80338164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Recent progress of resistive switching random access memory (RRAM)","authors":"Yi Wu, Shimeng Yu, X. Guan, H. Wong","doi":"10.1109/SNW.2012.6243331","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243331","url":null,"abstract":"This paper gives an overview of recent works on metal oxide resistive switching memory (RRAM). We explored the stochastic nature of resistive switching in metal oxide RRAM and a 2-D analytical solver was established to explain the switching parameter variations in HfOx-based RRAM. As an example of application beyond digital memory/storage, AlOx-based RRAM was explored for neuromorphic computing.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81278630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Simultaneous carrier transport enhancement and variability reduction in Si MOSFETs by insertion of partial monolayers of oxygen","authors":"R. Mears, N. Xu, N. Damrongplasit, H. Takeuchi, R. Stephenson, N. Cody, A. Yiptong, X. Huang, M. Hytha, Tsu-Jae King-Liu","doi":"10.1109/SNW.2012.6243326","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243326","url":null,"abstract":"We demonstrate simultaneous NMOS and PMOS high-field mobility enhancement and variability reduction by inserting partial monolayers of oxygen during silicon epitaxy of the channel layer.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75908871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Investigation on hump effects of L-shaped tunneling filed-effect transistors","authors":"Sang Wan Kim, W. Choi, Hyungjin Kim, Min-Chul Sun, H. Kim, Byung-Gook Park","doi":"10.1109/SNW.2012.6243306","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243306","url":null,"abstract":"In this paper, hump effects of L-shaped tunneling field-effect transistors (TFETs) have been investigated. It turns out that the hump effects are originated from the two different turn-on voltages (Vturn-on's). By using device simulation, the source junction design has been optimized in order to suppress the hump effects.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87090783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A novel gate-all-around ultra-thin p-channel poly-Si TFT functioning as transistor and flash memory with silicon nanocrystals","authors":"Hung-Bin Chen, Shih-Han Lin, Jia-Jiun Wu, Yung-Chun Wu, Chun-Yen Chang","doi":"10.1109/SNW.2012.6243321","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243321","url":null,"abstract":"A novel gate-all-around ultra-thin p-channel poly-Si TFT functioning as transistor and flash memory with silicon nanocrystals have been successfully demonstrated. The process is simple and mask free. For the 3-nm-thick channel devices, the S.S. of 88 mV/dec and Ion/Ioff ratio of more than 108 can be achieved. Extreme low applied voltage for band-to-band-tunneling-induced hot electron injection tunneling (BBHE) operation and excellent retention are proposed.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72808255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Charge sensing of a Si triple quantum dot system using single electron transistors","authors":"R. Mizokuchi, T. Kodera, K. Horibe, Y. Kawano, S. Oda","doi":"10.1109/SNW.2012.6243290","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243290","url":null,"abstract":"We fabricate a serial triple quantum dot (TQD) system, which is made on a silicon-on-insulator (SOI) wafer by dry etching and integrated with single electron transistors (SETs) as charge sensors. We observe charge transitions of a dot in the TQD in the characteristic of the charge sensor which is the furthest to the dot. It implies a SET charge sensor has a capability of sensing of all the charge transitions in TQD.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76861524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}