2012 IEEE Silicon Nanoelectronics Workshop (SNW)最新文献

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Device structure for the characterization of nanowire thermocouples 表征纳米线热电偶的器件结构
2012 IEEE Silicon Nanoelectronics Workshop (SNW) Pub Date : 2012-06-10 DOI: 10.1109/SNW.2012.6243307
G. Szakmany, P. Krenz, A. Orlov, G. Bernstein, W. Porod
{"title":"Device structure for the characterization of nanowire thermocouples","authors":"G. Szakmany, P. Krenz, A. Orlov, G. Bernstein, W. Porod","doi":"10.1109/SNW.2012.6243307","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243307","url":null,"abstract":"In order to demonstrate the feasibility of this approach, we report the measurements of the Seebeck coefficients of a palladium-gold and a palladium-chrome nanowire (70 nm wide and 50 nm thick) thermocouple. The thermocouple, heater, and thermometers were fabricated on top of 640 nm of thermally grown SiO2 on a silicon wafer using electron beam lithography and electron beam evaporation.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77734536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Bidirectional selection device characteristics of ultra-thin (<3nm) TiO2 layer for 3D vertically stackable ReRAM application 双向选择器件特性超薄(&#60;3nm) TiO2层用于3D垂直可堆叠ReRAM应用
2012 IEEE Silicon Nanoelectronics Workshop (SNW) Pub Date : 2012-06-10 DOI: 10.1109/SNW.2012.6243332
J. Woo, Jubong Park, Jungho Shin, G. Choi, Seonghyun Kim, Wootae Lee, Sangsu Park, Daeseok Lee, E. Cha, H. Hwang
{"title":"Bidirectional selection device characteristics of ultra-thin (&#60;3nm) TiO2 layer for 3D vertically stackable ReRAM application","authors":"J. Woo, Jubong Park, Jungho Shin, G. Choi, Seonghyun Kim, Wootae Lee, Sangsu Park, Daeseok Lee, E. Cha, H. Hwang","doi":"10.1109/SNW.2012.6243332","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243332","url":null,"abstract":"We propose the feasibility of bidirectional selection device characteristics in ultrathin (<;3nm) TiO<sub>2</sub> layer. We utilized the localized conducting path as virtual electrode to investigate device property at extremely scaled area. By using electrical method such as “forming” and “reset” processes in oxide, virtual electrode/sub-3nm-thick TiO<sub>2</sub>/virtual electrode structure was achieved. The measured current-voltage characteristics of fabricated device exhibited uniform bidirectional selection behavior with a high selectivity (~10<sup>5</sup>) and showed the feasibility of high current density (>;10<sup>6</sup>A/cm<sup>2</sup>).","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91463052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Graphene-diamond-silicon devices with increased current-carrying capacity: sp2-Carbon-sp3-Carbon-on-Silicon technology 增加载流能力的石墨烯-金刚石-硅器件:sp2-碳-sp3-碳-硅技术
2012 IEEE Silicon Nanoelectronics Workshop (SNW) Pub Date : 2012-06-10 DOI: 10.1109/SNW.2012.6243282
Jie Yu, Guanxiong Liu, A. Sumant, A. Balandin
{"title":"Graphene-diamond-silicon devices with increased current-carrying capacity: sp2-Carbon-sp3-Carbon-on-Silicon technology","authors":"Jie Yu, Guanxiong Liu, A. Sumant, A. Balandin","doi":"10.1109/SNW.2012.6243282","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243282","url":null,"abstract":"Graphene demonstrated potential for practical applications owing to its excellent electronic and thermal properties. Typical graphene field-effect transistors (FETs) and interconnects built on conventional SiO2/Si substrates reveal the breakdown current density on the order of 108 A/cm2, which is ~100× larger than the fundamental limit for the metals but still smaller than the maximum achieved in carbon nanotubes. It was discovered by some of us that graphene has excellent thermal conduction properties with the thermal conductivity K exceeding 2000 W/mK at room temperature [1]. Few-layer graphene largely preserves the heat conduction properties [2]. However, the thermally resistive SiO2, with the thermal conductivity in the range from 0.5 to 1.4 W/mK, creates a bottleneck for heat removal. The latter does not allow graphene to demonstrate its true current-carrying potential. We show that by replacing SiO2 with synthetic diamond one can substantially increase the current-carrying capacity of graphene to as high as ~ 20×108 A/cm2 under ambient conditions. The two-terminal and three-terminal top-gated graphene devices (see Figure 1) were fabricated on synthetic single-crystal diamond (SCD) and ultrananocrystalline diamond (UNCD). To ensure Si integration, the UNCD layers were grown at low temperatures compatible with Si CMOS technology [3]. Our results indicate that graphene's current-induced breakdown is thermally activated. It was found that the current carrying capacity of graphene can be improved not only on SCD but also on an inexpensive UNCD. The latter was attributed to the decreased thermal resistance of UNCD at elevated temperatures (see Figure 2). The obtained results are important for graphene's hetero-integration on Si substrates. The enhanced current-carrying capacity is beneficial for the proposed applications of graphene in interconnects and high-frequency transistors.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83445522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Rectifying characteristics and implementation of n-Si/HfO2 based devices for 1D1R-based cross-bar memory array 基于n-Si/HfO2器件的1d1r交叉棒存储阵列整流特性及实现
2012 IEEE Silicon Nanoelectronics Workshop (SNW) Pub Date : 2012-06-10 DOI: 10.1109/SNW.2012.6243357
F. Zhang, P. Huang, B. Chen, D. Yu, Y. Fu, L. Ma, B. Gao, L. Liu, X. Liu, J. Kang
{"title":"Rectifying characteristics and implementation of n-Si/HfO2 based devices for 1D1R-based cross-bar memory array","authors":"F. Zhang, P. Huang, B. Chen, D. Yu, Y. Fu, L. Ma, B. Gao, L. Liu, X. Liu, J. Kang","doi":"10.1109/SNW.2012.6243357","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243357","url":null,"abstract":"Excellent rectifying characteristics are demonstrated in the fab-friendly n-Si/HfO2/Ni/TiN devices with rectification ratio of >;107 and the driving current of 1mA as a 1D-like selector. The rectified unipolar switching behaviors are demonstrated in the 1D1R cell structured with a diode-like device of n-Si/HfO2/Ni/TiN (1D) and a unipolar RRAM of n+-Si/HfOx/Ni/TiN (1R). Based on the measured I-V characteristics, these excellent selection behavior can be implemented in the cross-bar memory array of >;64K bits RRAM with large read margin.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79543157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
4kb nonvolatile nanogap memory (NGpM) with 1 ns programming capability 4kb非易失性纳米隙存储器(NGpM),具有1ns编程能力
2012 IEEE Silicon Nanoelectronics Workshop (SNW) Pub Date : 2012-06-10 DOI: 10.1109/SNW.2012.6243334
T. Takahashi, S. Furuta, Y. Masuda, S. Kumaragurubaran, T. Sumiya, M. Ono, Y. Hayashi, T. Shimizu, H. Suga, M. Horikawa, Y. Naitoh
{"title":"4kb nonvolatile nanogap memory (NGpM) with 1 ns programming capability","authors":"T. Takahashi, S. Furuta, Y. Masuda, S. Kumaragurubaran, T. Sumiya, M. Ono, Y. Hayashi, T. Shimizu, H. Suga, M. Horikawa, Y. Naitoh","doi":"10.1109/SNW.2012.6243334","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243334","url":null,"abstract":"A 4k bits nonvolatile high-speed nanogap memory device was fabricated with a newly developed vertical nanogap structure and its memory characteristics were evaluated. The newly developed vertical nanogap structures realized controllable electrode gap and higher yield compared to the initial phase lateral type nanogap structure. The structures were integrated on a CMOS chip. The specially embedded measurement circuit revealed programming speed from a low resistance state to a high resistance state (from on to off state) to be 1 ns.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88190661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Charge-trap flash memory devices fabricated with nano-scale patterns on the Si3N4 trapping layer 在氮化硅捕获层上制备具有纳米尺度图案的电荷阱闪存器件
2012 IEEE Silicon Nanoelectronics Workshop (SNW) Pub Date : 2012-06-10 DOI: 10.1109/SNW.2012.6243350
H. An, Kyong Heon Kim, H. Kim, W. Cho, Tae Geun Kim
{"title":"Charge-trap flash memory devices fabricated with nano-scale patterns on the Si3N4 trapping layer","authors":"H. An, Kyong Heon Kim, H. Kim, W. Cho, Tae Geun Kim","doi":"10.1109/SNW.2012.6243350","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243350","url":null,"abstract":"We proposed a novel CTF memory structure with surface patterned Si3N4 trap layers, in order to enhance the memory window and the performance for ultra-high density CTF devices. Due to the enlargement of surface memory-trap densities, the CTF devices with nano-scale surface patterns on the Si3N4 trap layer by NSL showed increased memory windows and improved program properties. In addition, the reasonable reliability, including data retention of 10 years and endurance of 104 P/E cycles, was obtained.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83362617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Electronic band structures of graphene nanomeshes 石墨烯纳米网的电子能带结构
2012 IEEE Silicon Nanoelectronics Workshop (SNW) Pub Date : 2012-02-29 DOI: 10.1109/SNW.2012.6243363
R. Sako, N. Hasegawa, Hideaki Tsuchiya, M. Ogawa
{"title":"Electronic band structures of graphene nanomeshes","authors":"R. Sako, N. Hasegawa, Hideaki Tsuchiya, M. Ogawa","doi":"10.1109/SNW.2012.6243363","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243363","url":null,"abstract":"Graphene nanomesh (GNM) is a highly interconnected network of graphene nanoribbons (GNRs) in which the size of nanoholes and the distance between them can be controlled down to the sub-10 nm scale [1]. GNM can open up a band gap in a large sheet of graphene to creat a semiconducting thin film. Actually, it was demonstrated that GNM-based transistors provide driving currents nearly 100 times greater than individual GNR devices, with a comparable on-off current ratio [1]. Furthermore, for practical use, GNM lattices should be much easier to produce and handle than GNRs. Therefore, the GNMs with variable periodicity and neck width are expected to offer a possibility of band gap engineering and graphene electronic applications [2]. In this study, we investigate the electronic band structures of GNMs with various geometric configurations based on a tight-binding approach [3], and examine the roles of the edge formation and neck width on the band gap opening.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-02-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90262979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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