在氮化硅捕获层上制备具有纳米尺度图案的电荷阱闪存器件

2012 IEEE Silicon Nanoelectronics Workshop (SNW) Pub Date : 2012-06-10 DOI:10.1109/SNW.2012.6243350

H. An, Kyong Heon Kim, H. Kim, W. Cho, Tae Geun Kim

{"title":"在氮化硅捕获层上制备具有纳米尺度图案的电荷阱闪存器件","authors":"H. An, Kyong Heon Kim, H. Kim, W. Cho, Tae Geun Kim","doi":"10.1109/SNW.2012.6243350","DOIUrl":null,"url":null,"abstract":"We proposed a novel CTF memory structure with surface patterned Si3N4 trap layers, in order to enhance the memory window and the performance for ultra-high density CTF devices. Due to the enlargement of surface memory-trap densities, the CTF devices with nano-scale surface patterns on the Si3N4 trap layer by NSL showed increased memory windows and improved program properties. In addition, the reasonable reliability, including data retention of 10 years and endurance of 104 P/E cycles, was obtained.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Charge-trap flash memory devices fabricated with nano-scale patterns on the Si3N4 trapping layer\",\"authors\":\"H. An, Kyong Heon Kim, H. Kim, W. Cho, Tae Geun Kim\",\"doi\":\"10.1109/SNW.2012.6243350\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We proposed a novel CTF memory structure with surface patterned Si3N4 trap layers, in order to enhance the memory window and the performance for ultra-high density CTF devices. Due to the enlargement of surface memory-trap densities, the CTF devices with nano-scale surface patterns on the Si3N4 trap layer by NSL showed increased memory windows and improved program properties. In addition, the reasonable reliability, including data retention of 10 years and endurance of 104 P/E cycles, was obtained.\",\"PeriodicalId\":6402,\"journal\":{\"name\":\"2012 IEEE Silicon Nanoelectronics Workshop (SNW)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-06-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 IEEE Silicon Nanoelectronics Workshop (SNW)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SNW.2012.6243350\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SNW.2012.6243350","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 1

摘要

为了提高超高密度CTF器件的记忆窗口和性能，我们提出了一种具有表面图像化Si3N4陷阱层的新型CTF存储器结构。由于表面记忆陷阱密度的增加，NSL在Si3N4陷阱层上具有纳米级表面图案的CTF器件显示出内存窗口的增加和程序性能的改善。此外，还获得了合理的信度，包括10年的数据保留和104次P/E循环的耐久性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Charge-trap flash memory devices fabricated with nano-scale patterns on the Si3N4 trapping layer

We proposed a novel CTF memory structure with surface patterned Si3N4 trap layers, in order to enhance the memory window and the performance for ultra-high density CTF devices. Due to the enlargement of surface memory-trap densities, the CTF devices with nano-scale surface patterns on the Si3N4 trap layer by NSL showed increased memory windows and improved program properties. In addition, the reasonable reliability, including data retention of 10 years and endurance of 104 P/E cycles, was obtained.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2012 IEEE Silicon Nanoelectronics Workshop (SNW)

自引率

0.00%

发文量