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Innovative thermal energy harvesting for zero power electronics 创新的零功率电子热能收集
2012 IEEE Silicon Nanoelectronics Workshop (SNW) Pub Date : 2012-06-10 DOI: 10.1109/SNW.2012.6243313
S. Monfray, O. Puscasu, G. Savelli, U. Soupremanien, E. Ollier, C. Guérin, L. Fréchette, É. Léveillé, G. Mirshekari, C. Maitre, P. Coronel, K. Domanski, P. Grabiec, P. Ancey, D. Guyomar, V. Bottarel, G. Ricotti, F. Boeuf, F. Gaillard, T. Skotnicki
{"title":"Innovative thermal energy harvesting for zero power electronics","authors":"S. Monfray, O. Puscasu, G. Savelli, U. Soupremanien, E. Ollier, C. Guérin, L. Fréchette, É. Léveillé, G. Mirshekari, C. Maitre, P. Coronel, K. Domanski, P. Grabiec, P. Ancey, D. Guyomar, V. Bottarel, G. Ricotti, F. Boeuf, F. Gaillard, T. Skotnicki","doi":"10.1109/SNW.2012.6243313","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243313","url":null,"abstract":"Thermal gradients, commonly present in our environment (fluid lines, warm fronts, electronics) are sources of energy rarely used today. This paper aims to present innovative approaches of thin and/or flexible thermal energy harvesters for smart and autonomous sensor network applications. The harvester system will be based on the collaborative work of interrelated energy nodes/units, which will be either piezo-thermofluidic converters (use of rapid thermal cycles of a working fluid) or piezo-thermomechanic converters (use of the mechanical energy developed by rapid snapping of micro-switches). The two kinds of energy nodes convert a heat flux into storable electrical energy through a piezoelectric transducer. Miniaturization of the energy nodes will lead to increased thermal transfer rates and consequently increased harvested power. To effectively use thermal energy sources in varying environments, the nodes will be adaptive versus different thermal gradients (in a predefined temperature range) and will possibly influence each other. The concept is unique in the sense that it is based on a matrix structure of micro or mini energy nodes which will work together in a collective approach to optimize the harvested energy, and which do not require the use of radiators as classical Seebeck approach, thanks to the controlled thermal resistance. This opens the door to new properties and features of the object, with better performances. It could therefore be declined on flexible substrates, allowing conformability around the sources of potential heat for low power applications.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"31 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89908324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
Mechanisms of ambient dependent mobility degradation in the graphene MOSFETs on SiO2 substrate 二氧化硅衬底上石墨烯mosfet中随环境变化的迁移率退化机制
2012 IEEE Silicon Nanoelectronics Workshop (SNW) Pub Date : 2012-06-10 DOI: 10.1109/SNW.2012.6243362
Y. G. Lee, C. Kang, C. Cho, Y. H. Kim, H. Hwang, J. J. Kim, U. Jung, E. Park, M. W. Kim, B. H. Lee
{"title":"Mechanisms of ambient dependent mobility degradation in the graphene MOSFETs on SiO2 substrate","authors":"Y. G. Lee, C. Kang, C. Cho, Y. H. Kim, H. Hwang, J. J. Kim, U. Jung, E. Park, M. W. Kim, B. H. Lee","doi":"10.1109/SNW.2012.6243362","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243362","url":null,"abstract":"Two different mechanisms affecting the device instability and mobility degradation at graphene MOSFET on SiO2 substrate and their time constant, 40μsec and ~ 370μsec, have been identified. Oxygen/H2O reaction at the surface of graphene was identified as a major source of device hysteresis causing mobility degradation and device instability.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"24 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86859310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The interplay of self-heating effects and static RTF in nanowire transistors 纳米线晶体管中自热效应与静态RTF的相互作用
2012 IEEE Silicon Nanoelectronics Workshop (SNW) Pub Date : 2012-06-10 DOI: 10.1109/SNW.2012.6243294
D. Vasileska, A. Hossain, S. Goodnick
{"title":"The interplay of self-heating effects and static RTF in nanowire transistors","authors":"D. Vasileska, A. Hossain, S. Goodnick","doi":"10.1109/SNW.2012.6243294","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243294","url":null,"abstract":"The purpose of this work is to present the results of our current investigations of the influence of the negatively charged trap on the magnitude of the on-current for the case when in addition to the short-range Coulomb interactions, self-heating effects are incorporated in the theoretical model. The nanowire FET being simulated in this work has gate oxide 0.8 nm thick and the BOX is 10 nm thick. The dimensions of the silicon nanowire are: 10 nm channel length, 7 nm channel thickness and 10 nm channel width. For the thermal conductivity, that appears in the acoustic phonons energy balance solvers, we have taken the value from Li Shi measurements that correspond to wire with cross-section of 7x10 nm.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"61 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84805656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Silicon single-electron transfer devices: Ultimate control of electric charge 硅单电子转移装置:电荷的终极控制
2012 IEEE Silicon Nanoelectronics Workshop (SNW) Pub Date : 2012-06-10 DOI: 10.1109/SNW.2012.6243336
A. Fujiwara, G. Yamahata, K. Nishiguchi, G. Lansbergen, Y. Ono
{"title":"Silicon single-electron transfer devices: Ultimate control of electric charge","authors":"A. Fujiwara, G. Yamahata, K. Nishiguchi, G. Lansbergen, Y. Ono","doi":"10.1109/SNW.2012.6243336","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243336","url":null,"abstract":"In this paper we describe our recent efforts to develop SE transfer devices based on Si nanotechnology.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"1 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90185285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Band structure and electron transport in multi-junction graphene nanoribbons 多结石墨烯纳米带的能带结构和电子输运
2012 IEEE Silicon Nanoelectronics Workshop (SNW) Pub Date : 2012-06-10 DOI: 10.1109/SNW.2012.6243281
N. Hasegawa, R. Sako, H. Tsuchiya, M. Ogawa
{"title":"Band structure and electron transport in multi-junction graphene nanoribbons","authors":"N. Hasegawa, R. Sako, H. Tsuchiya, M. Ogawa","doi":"10.1109/SNW.2012.6243281","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243281","url":null,"abstract":"In this study, an electrical heterojunction consisting of multi-connected semiconducting and metallic graphene nanoribbons with armchair-edged configurations, is considered and discuss its basic properties by performing the electronic band structure calculations.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"40 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81873948","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
On the statistical trap-response (STR) method for characterizing random trap occupancy and NBTI fluctuation 统计陷阱-响应(STR)方法表征随机陷阱占用率和NBTI波动
2012 IEEE Silicon Nanoelectronics Workshop (SNW) Pub Date : 2012-06-10 DOI: 10.1109/SNW.2012.6243346
Jibin Zou, Changze Liu, Runsheng Wang, Xiaoqing Xu, Jinhua Liu, Hanming Wu, Yangyuan Wang, Ru Huang
{"title":"On the statistical trap-response (STR) method for characterizing random trap occupancy and NBTI fluctuation","authors":"Jibin Zou, Changze Liu, Runsheng Wang, Xiaoqing Xu, Jinhua Liu, Hanming Wu, Yangyuan Wang, Ru Huang","doi":"10.1109/SNW.2012.6243346","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243346","url":null,"abstract":"In nanoscale devices with only a few oxide traps, characterization of trap response during NBTI stress is challenging due to the stochastic nature of trapping/detrapping behavior. This paper successfully extends the statistical trap-response (STR) method from DC to AC device operation, for getting a full understanding of the trap occupancy probability and the aging-induced dynamic variations under DC and AC NBTI. The AC trap response and the AC NBTI fluctuations are found largely deviating from the DC case, indicating different physical mechanisms.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"3 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85754678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
New type steep-S device using the bipolar action 采用双极动作的新型陡s装置
2012 IEEE Silicon Nanoelectronics Workshop (SNW) Pub Date : 2012-06-10 DOI: 10.1109/SNW.2012.6243314
D. Hisamoto, S. Saito, A. Shima, H. Yoshimoto, K. Torii
{"title":"New type steep-S device using the bipolar action","authors":"D. Hisamoto, S. Saito, A. Shima, H. Yoshimoto, K. Torii","doi":"10.1109/SNW.2012.6243314","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243314","url":null,"abstract":"We have proposed an alternative approach for developing a steep subthreshold swing FET that is less than the theoretical diffusion-based limit of 60 mV/decade at room temperature. Instead of using a simple IGFET, we formed a complex device in a “single device” and worked it as a sub-circuit, which resulted in a steep subthreshold swing. We formed a tunnel junction in a drain diffusion layer of the MOSFET so that we could stuff a tunnel-injection bipolar, a resistor, and a MOSFET inside a single “scaled MOSFET”. We used device simulation to clarify the concept of “device complex”. Results showed a steep subthreshold swing even if the supply voltage was low (~0.2 V).","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"76 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74145321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High-frequency properties of Si single-electron transistor 硅单电子晶体管的高频特性
2012 IEEE Silicon Nanoelectronics Workshop (SNW) Pub Date : 2012-06-10 DOI: 10.1109/SNW.2012.6243339
H. Takenaka, M. Shinohara, T. Uchida, M. Arita, A. Fujiwara, Y. Ono, K. Nishiguchi, H. Inokawa, Y. Takahashi
{"title":"High-frequency properties of Si single-electron transistor","authors":"H. Takenaka, M. Shinohara, T. Uchida, M. Arita, A. Fujiwara, Y. Ono, K. Nishiguchi, H. Inokawa, Y. Takahashi","doi":"10.1109/SNW.2012.6243339","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243339","url":null,"abstract":"High-frequency limit of Si single-electron transistor (SET) is investigated. Since the SETs inevitably have tunnel barriers, the operation speed is thought to be low. To measure the high frequency properties of SETs, we employed their special rectification characteristics, which occurred due to the asymmetry of Coulomb diamond when alternating current voltage was applied to the drain terminal. By the use of the effect, we evaluated the high-frequency properties of Si SETs.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"2001 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78553580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Quantum transport property in FETs with deterministically implanted single-arsenic ions using single-ion implantation 用单离子注入确定注入单砷离子的场效应管的量子输运性质
2012 IEEE Silicon Nanoelectronics Workshop (SNW) Pub Date : 2012-06-10 DOI: 10.1109/SNW.2012.6243338
M. Hori, T. Shinada, F. Guagliardo, G. Ferrari, E. Prati
{"title":"Quantum transport property in FETs with deterministically implanted single-arsenic ions using single-ion implantation","authors":"M. Hori, T. Shinada, F. Guagliardo, G. Ferrari, E. Prati","doi":"10.1109/SNW.2012.6243338","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243338","url":null,"abstract":"We fabricated silicon transistors containing two and six arsenic ions implanted in one dimensional array along the channel by single-ion implantation method. The quantum transport was measured through the D0 and D- states of the arsenic ions at low temperature. We observed two different quantum transport regimes from the individual donor regime to the intermediate doping regime in which Hubbard bands are formed in agreement with the theoretical models. These results indicate that our deterministic single-ion doping method is more effective and reliable for single-dopant transistor development and pave the way towards single atom electronics for extended CMOS applications [12].","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"46 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72907700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
3-D stacked NAND flash memory having lateral bit-line layers and vertical gate 具有横向位线层和垂直栅极的3-D堆叠NAND闪存
2012 IEEE Silicon Nanoelectronics Workshop (SNW) Pub Date : 2012-06-10 DOI: 10.1109/SNW.2012.6243354
Ju-Wan Lee, M. Jeong, Byung-Gook Park, Hyungcheol Shin, Jang-Sik Lee
{"title":"3-D stacked NAND flash memory having lateral bit-line layers and vertical gate","authors":"Ju-Wan Lee, M. Jeong, Byung-Gook Park, Hyungcheol Shin, Jang-Sik Lee","doi":"10.1109/SNW.2012.6243354","DOIUrl":"https://doi.org/10.1109/SNW.2012.6243354","url":null,"abstract":"In this paper, we have studied a new 3-D stacked NAND flash memory structure and explained the fabrication sequence and key features of fabricated devices. Reasonable operation of the devices was shown in terms of ΔVth, retention and cycling characteristics. Moreover, the device characteristics were quite improved by removing the etch damage on the side surface (channel) of poly-Si BL layers when CDE process was adopted after etching the BL stack.","PeriodicalId":6402,"journal":{"name":"2012 IEEE Silicon Nanoelectronics Workshop (SNW)","volume":"124 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2012-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77343856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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