Bipolar/BiCMOS Circuits and Technology, 2004. Proceedings of the 2004 Meeting最新文献

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A SiGe dual-band dual-mode RF front end with a novel architecture for IEEE 802.11a/b/g wireless LAN applications 为IEEE 802.11a/b/g无线局域网应用提供了一种具有新颖架构的SiGe双频双模射频前端
Bipolar/BiCMOS Circuits and Technology, 2004. Proceedings of the 2004 Meeting Pub Date : 2004-12-13 DOI: 10.1109/BIPOL.2004.1365761
B. Banerjee, Chang-Ho Lee, B. Matinpour, J. Laskar
{"title":"A SiGe dual-band dual-mode RF front end with a novel architecture for IEEE 802.11a/b/g wireless LAN applications","authors":"B. Banerjee, Chang-Ho Lee, B. Matinpour, J. Laskar","doi":"10.1109/BIPOL.2004.1365761","DOIUrl":"https://doi.org/10.1109/BIPOL.2004.1365761","url":null,"abstract":"This paper presents a novel architecture for a RF front end for IEEE 802.11a/b/g wireless LAN. This architecture uses an on-chip frequency doubler for the 5 GHz band while bypassing it with a local oscillator (LO) buffer for the 2.4 GHz band. This allows the use of only one external frequency synthesizer to provide the LO for both the 5 GHz and 2.4 GHz bands. The MMIC, designed in 0.8-/spl mu/m SiGe bipolar technology with f/sub T/ of 50 GHz, consists of transmit and receive chains for both the 2.4 GHz and 5 GHz frequency bands. The transceiver consists of two switched gain LNAs, receive and transmit mixers, two transmit drivers, an LO doubler/buffer and power management and logic circuitry for selecting between transmit/receive, 2.4/5 GHz bands and high/low gain modes of operation. For a 3 V power supply, the overall power consumption for the transmit chain is 138 mW (both bands) and for the receive chain is between 78 mW and 102 mW for the two bands and two modes of operation.","PeriodicalId":447762,"journal":{"name":"Bipolar/BiCMOS Circuits and Technology, 2004. Proceedings of the 2004 Meeting","volume":"331 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122841878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Power semiconductor and IC technologies in audiovisual applications 功率半导体和集成电路技术在视听中的应用
Bipolar/BiCMOS Circuits and Technology, 2004. Proceedings of the 2004 Meeting Pub Date : 2004-12-13 DOI: 10.1109/BIPOL.2004.1365770
D. Kinzer
{"title":"Power semiconductor and IC technologies in audiovisual applications","authors":"D. Kinzer","doi":"10.1109/BIPOL.2004.1365770","DOIUrl":"https://doi.org/10.1109/BIPOL.2004.1365770","url":null,"abstract":"Modern class-D audio and plasma displays depend on high voltage IC technology and power transistors. 100-300 V BiCMOS level shifted gate drivers control 100 V trench MOSFETs and 300 V insulated gate bipolar transistors in thermally efficient, low inductance direct packages.","PeriodicalId":447762,"journal":{"name":"Bipolar/BiCMOS Circuits and Technology, 2004. Proceedings of the 2004 Meeting","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125738848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
AC and DC characteristics of carbon nanotube field-effect transistors 碳纳米管场效应晶体管的交直流特性
Bipolar/BiCMOS Circuits and Technology, 2004. Proceedings of the 2004 Meeting Pub Date : 2004-12-13 DOI: 10.1109/BIPOL.2004.1365777
J. Appenzeller
{"title":"AC and DC characteristics of carbon nanotube field-effect transistors","authors":"J. Appenzeller","doi":"10.1109/BIPOL.2004.1365777","DOIUrl":"https://doi.org/10.1109/BIPOL.2004.1365777","url":null,"abstract":"Recent results on the DC as well as AC characteristics of carbon nanotube field-effect transistors (CN-FETs) are presented. Experimental data is discussed in the context of an extended Schottky barrier model and the potential of CNFETs for high frequency applications is elucidated.","PeriodicalId":447762,"journal":{"name":"Bipolar/BiCMOS Circuits and Technology, 2004. Proceedings of the 2004 Meeting","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130781251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Physical modeling and alleviation of shallow-trench-isolation charging effects in silicon-on-insulator complementary bipolar technology 硅-绝缘子互补双极技术中浅沟隔离充电效应的物理模拟和缓解
Bipolar/BiCMOS Circuits and Technology, 2004. Proceedings of the 2004 Meeting Pub Date : 2004-12-13 DOI: 10.1109/BIPOL.2004.1365740
W. Yindeepol, R. Foote, J. De Santis, T. Krakowski, C. Bulucea
{"title":"Physical modeling and alleviation of shallow-trench-isolation charging effects in silicon-on-insulator complementary bipolar technology","authors":"W. Yindeepol, R. Foote, J. De Santis, T. Krakowski, C. Bulucea","doi":"10.1109/BIPOL.2004.1365740","DOIUrl":"https://doi.org/10.1109/BIPOL.2004.1365740","url":null,"abstract":"Oxide charging, adversely influencing PNP collector-base capacitance, has been observed and modeled physically in a complementary bipolar process that uses dielectric isolation. A practical solution to alleviate this effect is described along with trade-offs involved in process and device design.","PeriodicalId":447762,"journal":{"name":"Bipolar/BiCMOS Circuits and Technology, 2004. Proceedings of the 2004 Meeting","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116173858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Barrier effects in SiGe HBT: modeling of high-injection base current increase SiGe HBT中的阻挡效应:高注入基极电流增加的建模
Bipolar/BiCMOS Circuits and Technology, 2004. Proceedings of the 2004 Meeting Pub Date : 2004-12-13 DOI: 10.1109/BIPOL.2004.1365756
S. Frégonèse, T. Zimmer, C. Maneux, P. Sulima
{"title":"Barrier effects in SiGe HBT: modeling of high-injection base current increase","authors":"S. Frégonèse, T. Zimmer, C. Maneux, P. Sulima","doi":"10.1109/BIPOL.2004.1365756","DOIUrl":"https://doi.org/10.1109/BIPOL.2004.1365756","url":null,"abstract":"The HBT's parasitic energy band barrier formation, located at the hetero-interface, was investigated. Physical simulations show that additional base current increase in the high-injection regime is associated with the parasitic barrier formation. The charge calculation related to the parasitic barrier allows us to derive a model for the base current increase which is implemented into an electrical scalable compact model and applied on measurements.","PeriodicalId":447762,"journal":{"name":"Bipolar/BiCMOS Circuits and Technology, 2004. Proceedings of the 2004 Meeting","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126829886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Differential distributed amplifier and oscillator in SiGe BiCMOS using close-packed interleaved on-chip transmission lines 采用密排交错片上传输线的SiGe BiCMOS差分分布式放大器和振荡器
Bipolar/BiCMOS Circuits and Technology, 2004. Proceedings of the 2004 Meeting Pub Date : 2004-12-13 DOI: 10.1109/BIPOL.2004.1365748
Drew Guckenberger, Kevin T. Kornegay
{"title":"Differential distributed amplifier and oscillator in SiGe BiCMOS using close-packed interleaved on-chip transmission lines","authors":"Drew Guckenberger, Kevin T. Kornegay","doi":"10.1109/BIPOL.2004.1365748","DOIUrl":"https://doi.org/10.1109/BIPOL.2004.1365748","url":null,"abstract":"A monolithic differential distributed amplifier using close-packed, shielded, meandered transmission lines and a delay-matched rotationally symmetric amplifier cell is implemented using a SiGe BiCMOS process with an f/sub T/ of 120 GHz. A broadband differential power gain of 7.5 dB is achieved with a bandwidth of 25 GHz, while consuming 30 mA from a 3.3 V supply. The amplifier can also be configured as a differential oscillator by connecting the input and output pads with wire bonds. This results in an oscillation frequency of 9.2 GHz with a phase noise of -103 dBc/Hz at a 1 MHz offset and single-ended output power of -6 dBm.","PeriodicalId":447762,"journal":{"name":"Bipolar/BiCMOS Circuits and Technology, 2004. Proceedings of the 2004 Meeting","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132711170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Experimental verification of substrate coupling in a high-gain 30 Gb/s SiGe amplifier 高增益30gb /s SiGe放大器中衬底耦合的实验验证
Bipolar/BiCMOS Circuits and Technology, 2004. Proceedings of the 2004 Meeting Pub Date : 2004-12-13 DOI: 10.1109/BIPOL.2004.1365798
W. Steiner, H. Rein, J. Berntgen
{"title":"Experimental verification of substrate coupling in a high-gain 30 Gb/s SiGe amplifier","authors":"W. Steiner, H. Rein, J. Berntgen","doi":"10.1109/BIPOL.2004.1365798","DOIUrl":"https://doi.org/10.1109/BIPOL.2004.1365798","url":null,"abstract":"n e influence of substrate coupling on the performance of a limiting 30 Gbls SiCe amplifier with a maximum ( n o n h e a r ) transimpedance as high as 25 kR has been veri6ed hy measurements. Several techniques for noisecoupling suppression had to be applied simultaneously to ohfain reliable operation at high input sensitirity.","PeriodicalId":447762,"journal":{"name":"Bipolar/BiCMOS Circuits and Technology, 2004. Proceedings of the 2004 Meeting","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124061361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Optimisation of LNA and PA circuits for a 1.8 V BiCMOS Si Bluetooth transceiver 1.8 V BiCMOS Si蓝牙收发器LNA和PA电路的优化
Bipolar/BiCMOS Circuits and Technology, 2004. Proceedings of the 2004 Meeting Pub Date : 2004-12-13 DOI: 10.1109/BIPOL.2004.1365744
E. van der Heijden, H. Veenstra
{"title":"Optimisation of LNA and PA circuits for a 1.8 V BiCMOS Si Bluetooth transceiver","authors":"E. van der Heijden, H. Veenstra","doi":"10.1109/BIPOL.2004.1365744","DOIUrl":"https://doi.org/10.1109/BIPOL.2004.1365744","url":null,"abstract":"In Bluetooth transceiver ICs, sharing transmitter output with receiver input pins is a major difficulty, often requiring off-chip switches. A design procedure optimising this interface is explained and demonstrated.","PeriodicalId":447762,"journal":{"name":"Bipolar/BiCMOS Circuits and Technology, 2004. Proceedings of the 2004 Meeting","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116868999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Lateral and vertical scaling of a QSA HBT for a 0.13/spl mu/m 200GHz SiGe:C BiCMOS technology 用于0.13/spl mu/m 200GHz SiGe:C BiCMOS技术的QSA HBT横向和纵向缩放
Bipolar/BiCMOS Circuits and Technology, 2004. Proceedings of the 2004 Meeting Pub Date : 2004-12-13 DOI: 10.1109/BIPOL.2004.1365787
S. Van Huylenbroeck, A. Sibaja-Hernandez, A. Piontek, L. J. Choi, M.W. Xu, N. Ouassif, F. Vleugels, K. van Wichelen, L. Witters, E. Kunnen, P. Leray, K. Devriendt, X. Shi, R. Loo, S. Decoutere
{"title":"Lateral and vertical scaling of a QSA HBT for a 0.13/spl mu/m 200GHz SiGe:C BiCMOS technology","authors":"S. Van Huylenbroeck, A. Sibaja-Hernandez, A. Piontek, L. J. Choi, M.W. Xu, N. Ouassif, F. Vleugels, K. van Wichelen, L. Witters, E. Kunnen, P. Leray, K. Devriendt, X. Shi, R. Loo, S. Decoutere","doi":"10.1109/BIPOL.2004.1365787","DOIUrl":"https://doi.org/10.1109/BIPOL.2004.1365787","url":null,"abstract":"A 200 GHz F/sub t/ SiGe:C HBT has been integrated into a 0.13 /spl mu/m BiCMOS technology. A previous generation low complexity quasi self-aligned architecture (QSA) is scaled down both in a lateral and vertical way. Lateral sizing is obtained by using present-day step and scan tools. Vertical sizing is achieved by reducing the thermal budget of the active module and by an aggressive scaling of the SiGe:C base epitaxial layer. A deep trench module, featuring a thick oxide liner, has been developed. Excellent DC parameters and peak Ft/Fmax values of 200/160 GHz are demonstrated. The CMOS device characteristics remain unchanged by applying low thermal budget processing in the bipolar module.","PeriodicalId":447762,"journal":{"name":"Bipolar/BiCMOS Circuits and Technology, 2004. Proceedings of the 2004 Meeting","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126035803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Ultra high frequency static dividers > 150 GHz in a narrow mesa InGaAs/InP DHBT technology 超高频静态分频器> 150ghz窄台InGaAs/InP DHBT技术
Bipolar/BiCMOS Circuits and Technology, 2004. Proceedings of the 2004 Meeting Pub Date : 2004-12-13 DOI: 10.1109/BIPOL.2004.1365773
Z. Griffith, M. Dahlström, M. Rodwell, M. Urteaga, Richard Pierson, P. Rowell, Bobby Brar, Sangmin Lee, Nguyen Nguyen, Chanh Nguyen
{"title":"Ultra high frequency static dividers > 150 GHz in a narrow mesa InGaAs/InP DHBT technology","authors":"Z. Griffith, M. Dahlström, M. Rodwell, M. Urteaga, Richard Pierson, P. Rowell, Bobby Brar, Sangmin Lee, Nguyen Nguyen, Chanh Nguyen","doi":"10.1109/BIPOL.2004.1365773","DOIUrl":"https://doi.org/10.1109/BIPOL.2004.1365773","url":null,"abstract":"A static frequency divider with a maximum clock frequency >150 GHz was designed and fabricated in a narrow mesa InP/In/sub 0.53/Ga/sub 0.47/As/InP DHBT technology. The divider operation is fully static, operating from f/sub dk/ = 3 GHz to 152.0 GHz while dissipating 594.7 mW of power in the circuit core from a -4.07 V supply. The circuit employs single-buffered emitter coupled logic (ECL) and inductive peaking. The transistors have an emitter junction width of 0.5 /spl mu/m and a 3.0 collector-to-emitter area ratio. A microstrip wiring environment is employed for high interconnect density, and to minimize resonances and impedance mismatch at frequencies >100 GHz.","PeriodicalId":447762,"journal":{"name":"Bipolar/BiCMOS Circuits and Technology, 2004. Proceedings of the 2004 Meeting","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125118098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 29
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