Ultra high frequency static dividers > 150 GHz in a narrow mesa InGaAs/InP DHBT technology

Abstract

A static frequency divider with a maximum clock frequency >150 GHz was designed and fabricated in a narrow mesa InP/In/sub 0.53/Ga/sub 0.47/As/InP DHBT technology. The divider operation is fully static, operating from f/sub dk/ = 3 GHz to 152.0 GHz while dissipating 594.7 mW of power in the circuit core from a -4.07 V supply. The circuit employs single-buffered emitter coupled logic (ECL) and inductive peaking. The transistors have an emitter junction width of 0.5 /spl mu/m and a 3.0 collector-to-emitter area ratio. A microstrip wiring environment is employed for high interconnect density, and to minimize resonances and impedance mismatch at frequencies >100 GHz.