Z. Griffith, M. Dahlström, M. Rodwell, M. Urteaga, Richard Pierson, P. Rowell, Bobby Brar, Sangmin Lee, Nguyen Nguyen, Chanh Nguyen
{"title":"超高频静态分频器> 150ghz窄台InGaAs/InP DHBT技术","authors":"Z. Griffith, M. Dahlström, M. Rodwell, M. Urteaga, Richard Pierson, P. Rowell, Bobby Brar, Sangmin Lee, Nguyen Nguyen, Chanh Nguyen","doi":"10.1109/BIPOL.2004.1365773","DOIUrl":null,"url":null,"abstract":"A static frequency divider with a maximum clock frequency >150 GHz was designed and fabricated in a narrow mesa InP/In/sub 0.53/Ga/sub 0.47/As/InP DHBT technology. The divider operation is fully static, operating from f/sub dk/ = 3 GHz to 152.0 GHz while dissipating 594.7 mW of power in the circuit core from a -4.07 V supply. The circuit employs single-buffered emitter coupled logic (ECL) and inductive peaking. The transistors have an emitter junction width of 0.5 /spl mu/m and a 3.0 collector-to-emitter area ratio. A microstrip wiring environment is employed for high interconnect density, and to minimize resonances and impedance mismatch at frequencies >100 GHz.","PeriodicalId":447762,"journal":{"name":"Bipolar/BiCMOS Circuits and Technology, 2004. Proceedings of the 2004 Meeting","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"29","resultStr":"{\"title\":\"Ultra high frequency static dividers > 150 GHz in a narrow mesa InGaAs/InP DHBT technology\",\"authors\":\"Z. Griffith, M. Dahlström, M. Rodwell, M. Urteaga, Richard Pierson, P. Rowell, Bobby Brar, Sangmin Lee, Nguyen Nguyen, Chanh Nguyen\",\"doi\":\"10.1109/BIPOL.2004.1365773\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A static frequency divider with a maximum clock frequency >150 GHz was designed and fabricated in a narrow mesa InP/In/sub 0.53/Ga/sub 0.47/As/InP DHBT technology. The divider operation is fully static, operating from f/sub dk/ = 3 GHz to 152.0 GHz while dissipating 594.7 mW of power in the circuit core from a -4.07 V supply. The circuit employs single-buffered emitter coupled logic (ECL) and inductive peaking. The transistors have an emitter junction width of 0.5 /spl mu/m and a 3.0 collector-to-emitter area ratio. A microstrip wiring environment is employed for high interconnect density, and to minimize resonances and impedance mismatch at frequencies >100 GHz.\",\"PeriodicalId\":447762,\"journal\":{\"name\":\"Bipolar/BiCMOS Circuits and Technology, 2004. Proceedings of the 2004 Meeting\",\"volume\":\"23 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-12-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"29\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Bipolar/BiCMOS Circuits and Technology, 2004. Proceedings of the 2004 Meeting\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/BIPOL.2004.1365773\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Bipolar/BiCMOS Circuits and Technology, 2004. Proceedings of the 2004 Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/BIPOL.2004.1365773","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Ultra high frequency static dividers > 150 GHz in a narrow mesa InGaAs/InP DHBT technology
A static frequency divider with a maximum clock frequency >150 GHz was designed and fabricated in a narrow mesa InP/In/sub 0.53/Ga/sub 0.47/As/InP DHBT technology. The divider operation is fully static, operating from f/sub dk/ = 3 GHz to 152.0 GHz while dissipating 594.7 mW of power in the circuit core from a -4.07 V supply. The circuit employs single-buffered emitter coupled logic (ECL) and inductive peaking. The transistors have an emitter junction width of 0.5 /spl mu/m and a 3.0 collector-to-emitter area ratio. A microstrip wiring environment is employed for high interconnect density, and to minimize resonances and impedance mismatch at frequencies >100 GHz.