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2009 IEEE 8th International Conference on ASIC最新文献

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A novel fast-settling ADPLL architecture with frequency tuning word presetting and calibration 一种具有频率调谐字预置和校准的新型快速稳定ADPLL结构
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351165
Weicheng Zhang, Xuan Dai, J. Jin, Jianjun J. Zhou
{"title":"A novel fast-settling ADPLL architecture with frequency tuning word presetting and calibration","authors":"Weicheng Zhang, Xuan Dai, J. Jin, Jianjun J. Zhou","doi":"10.1109/ASICON.2009.5351165","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351165","url":null,"abstract":"A time domain behavior modeling for fast-settling all digital phase-locked-loop (ADPLL) is proposed. By using the frequency presetting and adaptive bandwidth algorithm, this ADPLL can lock within 2µs according to the Simulink behavior simulation results. A digital frequency presetting module with self-calibration is presented for the frequency presetting method. An improved digital phase/frequency detector and locking detector are also included for the enhancement of fast settling1.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127812980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Accelerating PCG power/ground network solver on GPGPU 在GPGPU上加速PCG电源/地网络求解
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351330
Yici Cai, Jin Shi
{"title":"Accelerating PCG power/ground network solver on GPGPU","authors":"Yici Cai, Jin Shi","doi":"10.1109/ASICON.2009.5351330","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351330","url":null,"abstract":"Currently fast and precise P/G (power/ground) solvers are critical for robust P/G designs, but traditional serial P/G solvers are somewhat incapable of millions of nodes in P/G. In spite of powerful computation capability of parallel hardware, paralleled P/G solvers are far from prevailing, especially on complicated special hardware. We anticipated it, and studied on parallelizing and accelerating P/G solvers on GPU. In our work, we developed a PCG(Preconditioned Conjugate Gradient)-based P/G solver on the CUDA platform for structured P/G network, and identified advantages as well as constraints from GPU architecture. Our PCG-GPU solver can be up to 40 times faster than SuperLU, and also outperform multi-grid based solver on GPU.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"189 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134634968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Large-scale analog/RF performance modeling by statistical regression 大规模模拟/射频性能统计回归建模
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351329
Xin Li
{"title":"Large-scale analog/RF performance modeling by statistical regression","authors":"Xin Li","doi":"10.1109/ASICON.2009.5351329","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351329","url":null,"abstract":"In this paper, we introduce several large-scale modeling techniques to analyze the high-dimensional, strongly-nonlinear performance variability observed in nanoscale manufacturing technologies. Our goal is to solve a large number of (e.g., 10<sup>4</sup>∼10<sup>6</sup>) model coefficients from a small set of (e.g., 10<sup>2</sup>∼10<sup>3</sup>) sampling points without over-fitting. This is facilitated by exploiting the underlying sparsity of model coefficients. Our circuit example designed in a commercial 65nm process demonstrates that the proposed techniques achieve 25× speedup compared with the traditional response surface modeling<sup>1</sup>.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133806511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Study of Q factor and loop delay effects of a continuous-time Δ Σ AD modulator 连续时间Δ Σ AD调制器的Q因子和环路延迟效应研究
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351486
Haijun Lin, A. Motozawa, P. Lo Ré, K. Iizuka, H. Kobayashi, H. San
{"title":"Study of Q factor and loop delay effects of a continuous-time Δ Σ AD modulator","authors":"Haijun Lin, A. Motozawa, P. Lo Ré, K. Iizuka, H. Kobayashi, H. San","doi":"10.1109/ASICON.2009.5351486","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351486","url":null,"abstract":"This paper describes the design and analysis of a continuous-time bandpass ΔΣ AD modulator for RF sampling. We determined the SNDR degradation due to finite Q value of the loop resonator, and due to excess loop delay (ELD). SNDR was improved by 20 dB by adding a digital filter which compensates for the effect of finite Q value, and SNDR was further improved by 20 dB by feedforward with parameters optimized to compensate for ELD. We have confirmed the effectiveness of the digital filter and feedforward proposals using Matlab and SPICE simulations.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115188959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
CMOL cell assignment based on dynamic interchange 基于动态交换的CMOL单元分配
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351545
Zhufei Chu, Yinshui Xia, Lunyao Wang, Meiqun Hu
{"title":"CMOL cell assignment based on dynamic interchange","authors":"Zhufei Chu, Yinshui Xia, Lunyao Wang, Meiqun Hu","doi":"10.1109/ASICON.2009.5351545","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351545","url":null,"abstract":"A new method based on dynamic interchange for cell assignment task of CMOL, a hybrid integrated circuit architecture, is proposed. In this paper, we first transform AND/OR/NOT gates composed of logic circuits into NOT gates and two inputs NOR gates, and then map the NOR/NOT gates to CMOL cells. During mapping process, we first allocate adequate CMOL cell resources and then randomly map the gates to the CMOL cells, which can satisfy the architecture demand and require no overlap between cells. Then we adjust the gates by interchanging and inserting buffers for long distance gate pair. Experiment results on MCNC benchmark show that the proposed approach can result in faster running time than prior approaches1.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"252 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115619376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Tuning of a capacitorless bandpass biquad through sequentially trained ANN 通过顺序训练的人工神经网络调谐无电容带通双路电路
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351457
Montira Moonngam, R. Chaisricharoen, B. Chipipop
{"title":"Tuning of a capacitorless bandpass biquad through sequentially trained ANN","authors":"Montira Moonngam, R. Chaisricharoen, B. Chipipop","doi":"10.1109/ASICON.2009.5351457","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351457","url":null,"abstract":"The sequential trained artificial neural network (ANN) based on updated training sets is successfully deployed to tune a capacitorless all-OTA bandpass biquad. The training set contains less than a few tens samples which are selected from predefine bias points that are closed to the desired biquad requirement. To limit training time, the less complex ANN is recommended. Feasibility of a biquad requirement is easily indicated by observing the maximum error of the worst element in an initial training set. A second-order bandpass requirement, centered at 406.2 MHz, is successfully tuned as a sample. The proposed feasibility analysis and tuning process are tested with one hundred random bandpass requirements. As there is no indication of type-I and type-II errors, the proposed process is considered very efficient1.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124100436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The verification of the substrate mathematics model and optimization of the substrate noise canceling technique in mixed signal ICs 混合信号集成电路中衬底数学模型的验证和衬底消噪技术的优化
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351218
Dongfang Cheng, Wenrong Yang, Jiongming Wang
{"title":"The verification of the substrate mathematics model and optimization of the substrate noise canceling technique in mixed signal ICs","authors":"Dongfang Cheng, Wenrong Yang, Jiongming Wang","doi":"10.1109/ASICON.2009.5351218","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351218","url":null,"abstract":"The substrate noise becomes more serious with the increasing frequency and decreasing process geometries. In this paper, a mathematics model of the substrate noise will be proposed. The current methods for solving the substrate noise will be analyzed using the model, and a new method is proposed based on the inverse relationship between the varying voltage of the power supply line and the one of ground line. In this method, there are two important units, which are high-pass filter and adder circuit. The noise is reduced by 26dB, compared with triple-well techniques.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124142372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Millimeter-wave CMOS circuits for a high data rate wireless transceiver 用于高数据速率无线收发器的毫米波CMOS电路
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351320
T. N. Nguyen, Seong-Gwon Lee, Sang-Hyun Hwang, Jong‐Wook Lee, Byung-sung Kim
{"title":"Millimeter-wave CMOS circuits for a high data rate wireless transceiver","authors":"T. N. Nguyen, Seong-Gwon Lee, Sang-Hyun Hwang, Jong‐Wook Lee, Byung-sung Kim","doi":"10.1109/ASICON.2009.5351320","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351320","url":null,"abstract":"This paper presents millimeter-wave CMOS building blocks for a high date rate wireless transceiver. The results include measured data for a 40–50 GHz broad-band low noise amplifier, a 40 GHz tuned power amplifier, and an 18 GHz voltage controlled oscillator. Also, simulation results for a 22 GHz multi-modulus prescaler is presented for implementing phase locked loop. The circuits were fabricated 0.13 µ m CMOS process. The measured results showed good agreement with simulation data demonstrating good modeling accuracy of CMOS active and passive devices for millimeter-wave applications.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114415983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design of low-voltage high performance CMOS-Current feedback amplifier using indirect feedback compensated Op-Amp 采用间接反馈补偿运算放大器的低压高性能cmos电流反馈放大器的设计
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351474
R. Nandwana, Mahima Arrawatia, Nilesh Goel
{"title":"Design of low-voltage high performance CMOS-Current feedback amplifier using indirect feedback compensated Op-Amp","authors":"R. Nandwana, Mahima Arrawatia, Nilesh Goel","doi":"10.1109/ASICON.2009.5351474","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351474","url":null,"abstract":"In this paper low-voltage high performance CMOS Current Feedback Amplifier is designed using indirect feedback compensated operational amplifier and the results are compared with the existing topology. The Operational-Amplifier used has the open loop gain of 101.8 dB with 25ns settling time, unity gain bandwidth 169.8 MHz, phase margin 70° with rail to rail output swing. The CMOS-Current Feedback Amplifier designed using this Operational-Amplifier has nearly gain independent bandwidth with settling time observed as 44 ns and slew rate increment up to 20V/µs. The circuit is designed at 0.18µm Digital CMOS process with supply voltage 1.8 volt.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117334971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Dynamic context management for coarse-grained reconfigurable array DSP architecture 粗粒度可重构阵列DSP体系结构的动态上下文管理
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351603
Yanliang Liu, Pengyu Dai, Xin'an Wang, Xing Zhang, Lai Wei, Yan Zhou, Yachun Sun
{"title":"Dynamic context management for coarse-grained reconfigurable array DSP architecture","authors":"Yanliang Liu, Pengyu Dai, Xin'an Wang, Xing Zhang, Lai Wei, Yan Zhou, Yachun Sun","doi":"10.1109/ASICON.2009.5351603","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351603","url":null,"abstract":"This paper proposes a novel technique of dynamic context management scheme for coarse-grained reconfigurable array DSP architecture, which effectively reduces the power consumption and speedup reconfigurable process. The technique permits background loading of configuration data without interrupting the regular execution, overlapping computation with reconfiguration. And stored configurations can be switched dramatically reducing reconfiguration overhead if the next configuration is present in one of the alternate contexts. The proposed technique has been verified in ReMAP (Reconfigurable Multi-media Array Processors) with the Discrete Cosine Transform (DCT) of H.264 and its performance exceed other DSP and multimedia extension architectures by 1.2x to 6.2x. ReMAP was fabricated with SMIC's 0.18um CMOS process mainly for multi-media applications1.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"141 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116276341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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