A novel fast-settling ADPLL architecture with frequency tuning word presetting and calibration

Abstract

A time domain behavior modeling for fast-settling all digital phase-locked-loop (ADPLL) is proposed. By using the frequency presetting and adaptive bandwidth algorithm, this ADPLL can lock within 2µs according to the Simulink behavior simulation results. A digital frequency presetting module with self-calibration is presented for the frequency presetting method. An improved digital phase/frequency detector and locking detector are also included for the enhancement of fast settling1.