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2009 IEEE 8th International Conference on ASIC最新文献

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Multi-voltage and level-shifter assignment driven floorplanning 多电压和电平转换分配驱动的地板规划
2009 IEEE 8th International Conference on ASIC Pub Date : 2014-02-12 DOI: 10.1109/ASICON.2009.5351219
Bei Yu, Sheqin Dong, S. Goto
{"title":"Multi-voltage and level-shifter assignment driven floorplanning","authors":"Bei Yu, Sheqin Dong, S. Goto","doi":"10.1109/ASICON.2009.5351219","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351219","url":null,"abstract":"As technology scales, low power design has become a significant requirement for SOC designers. Among the existing techniques, Multiple-Supply Voltage (MSV) is a popular and effective method to reduce both dynamic and static power. Besides, level shifters consume area and delay, and should be considered during floorplanning. In this paper, we present a new floorplanning system, called MVLSAF, to solve multi-voltage and level shifter assignment problem. We use a convex cost network flow algorithm to assign arbitrary number of legal working voltages and a minimum cost flow algorithm to handle level-shifter assignment. The experimental results show MVLSAF is effective1.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126252824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Formal verification of mixed-signal circuits using extended PSL 使用扩展PSL的混合信号电路的正式验证
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351231
Meng Zhang, Deyuan Gao, Xiaoya Fan
{"title":"Formal verification of mixed-signal circuits using extended PSL","authors":"Meng Zhang, Deyuan Gao, Xiaoya Fan","doi":"10.1109/ASICON.2009.5351231","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351231","url":null,"abstract":"As an alternative approach, analyzing hybrid property, the formal method using extended PSL to express specification of mixed-signal circuits is addressed in this paper. With the ability to modeling discrete and continuous dynamic system, Hybrid Automata is adopted in verification of mixed-signal circuits. We extend the PSL to HAPSL (Hybrid Automata Based PSL) with Hybrid Automata, and define EBNF grammar for the syntax of HAPSL. The continuous temporal property and probabilistic property of mixed-signal circuit can be abstracted by HAPSL. Model Checking is proposed as a formal verifying methodology, in which an on-the- fly checking is preformed for the continuous temporal property, and the checking of probabilistic property is based on hypothesis test. We illustrated this method by analyzing two mixed-signal circuits. The specification of circuit that depends on continuous variables and stochastic process is expressed by HAPSL sentences.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115403365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Framework for statistical analysis of homogeneous multicore power grid networks 同质多核电网统计分析框架
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351259
Guanglei Liu, Jeffrey Fan
{"title":"Framework for statistical analysis of homogeneous multicore power grid networks","authors":"Guanglei Liu, Jeffrey Fan","doi":"10.1109/ASICON.2009.5351259","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351259","url":null,"abstract":"In this paper, we propose a framework to analyze the large-scaled multicore power grid network statistically by first building a simplified multicore power supply distribution model. We then apply the Modified Nodal Analysis (MNA) method on a simplified power gird circuit. Under such a framework, most statistical approaches, including Monte Carlo (MC), Importance Sampling, and Stochastic Spectrum Analysis, can be applied to analyze the process-induced variation of homogeneous multicore power grid networks. In the experiment, we focus on the subthreshold leakage current variations, which are modeled as lognormal distribution random variables, by using MC approach as an example to demonstrate the feasibility of such a framework.1","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115448901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The gate-bias influence for ESD characteristic of NMOS 栅极偏置对NMOS ESD特性的影响
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351505
Juan Liu, Hang Fan, Jianguo Li, Lingli Jiang, Bo Zhang
{"title":"The gate-bias influence for ESD characteristic of NMOS","authors":"Juan Liu, Hang Fan, Jianguo Li, Lingli Jiang, Bo Zhang","doi":"10.1109/ASICON.2009.5351505","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351505","url":null,"abstract":"The positive and negative gate-bias effect on ESD robustness of NMOS devices are analyzed respectively in this paper. The influence of gate-bias have been simulated by ISE TCAD and discussed. The simulation results indicate that the triggering voltage fell from 10.46V to 7.8V with the negative gate bias changed from 0V to −10V, and reduced from 10.46V to 5.92V with the positive gate bias changed from 0V to 3V. Under appropriate gate bias, the ESD protection devices can obtain lower Vt1 and higher Vt2. It gives benefit of triggering the large-dimension MOS uniformly, which can improve ESD robustness directly.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115694060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Quantum-mechanical study on the electron effective mobility of surrounding-gate nMOSFETs 围绕栅nmosfet电子有效迁移率的量子力学研究
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351286
Guangxi Hu, Ran Liu, T. Tang, Lingli Wang, Z. Qiu
{"title":"Quantum-mechanical study on the electron effective mobility of surrounding-gate nMOSFETs","authors":"Guangxi Hu, Ran Liu, T. Tang, Lingli Wang, Z. Qiu","doi":"10.1109/ASICON.2009.5351286","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351286","url":null,"abstract":"As metal - oxide - semiconductor field-effect transistors (MOSFETs) down scaling progresses into the nanometer regime, quantum mechanical effects are becoming more and more significant. In this work, a model for the surrounding-gate (SG) nMOSFET is developed. The Schrödinger equation is solved analytically and some of the results are verified via simulations. We find that the percentage of the electrons with a lighter conductivity mass increases as the temperature decreases, or as the gate voltage reduces. These imply that low temperature and low gate voltage will enhance the electron effective mobility, which is good for the device performance.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121032926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
VLSI design of resource shared complex-QMF bank for HE-AAC decoder HE-AAC译码器资源共享复合物- qmf库的VLSI设计
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351287
Junqiao Huang, Gaoming Du, Duoli Zhang, Y. Song, Luofeng Geng, M. Gao
{"title":"VLSI design of resource shared complex-QMF bank for HE-AAC decoder","authors":"Junqiao Huang, Gaoming Du, Duoli Zhang, Y. Song, Luofeng Geng, M. Gao","doi":"10.1109/ASICON.2009.5351287","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351287","url":null,"abstract":"A VLSI design of complex Quadrature Mirror Filterbank (QMF) for MPEG-4 High Efficiency Advanced Audio Coding (MPEG-4 HE-AAC) decoder using resource-sharing technique is proposed. The algorithm that uses conventional discrete cosine transform of type IV(DCT-IV) to optimize complex-QMF is derived in this paper. By using the proposed algorithm, the VLSI design of complex valued analysis quadrature mirror filterbank (complex-AQMF) and synthesis quadrature mirror filterbank (complex-SQMF) can improve resource efficiently by sharing the same DCT module. Experiment results show that the computational complexity of the complex-QMF can be reduced up to 8.59%, the VLSI architecture of the proposed algorithm can save about 53% of area and 50% memory due to the shared resources of DCT-IV.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127246374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Low-complexity architecture of RS decoder for CMMB system CMMB系统RS解码器的低复杂度结构
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351525
Kun Guo, Yong Hei, Shushan Qiao
{"title":"Low-complexity architecture of RS decoder for CMMB system","authors":"Kun Guo, Yong Hei, Shushan Qiao","doi":"10.1109/ASICON.2009.5351525","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351525","url":null,"abstract":"Based on the Berlekamp-Massey algorithm, a low-complexity VLSI architecture of Reed-Solomon decoder for CMMB is presented in this paper. The proposed scheme has a folded systolic architecture, in which both error-locator and the error-evaluator can be computed in a single array of processors. With the folding property of the systolic array architecture, the number of the multipliers and the adders are reduced drastically. The architecture chooses 8 as the folding factor, as a result, 80% fewer multipliers and adders are used in the proposed architecture than in the RiBM architecture. The reduction in the number of multipliers and adders lead to smaller silicon area and lower power consumption. The proposed RS (240,224) decoder design is implemented and fabricated in HJTC 0.18µm 1P6M CMOS technology.1","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127331057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design of 16-bit 400MSPS current steering D/A converter 16位400MSPS电流转向数模转换器的设计
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351181
Fu Dongbing, Zhu Dongmei, Zhou Shu-tao, L. Kaicheng
{"title":"Design of 16-bit 400MSPS current steering D/A converter","authors":"Fu Dongbing, Zhu Dongmei, Zhou Shu-tao, L. Kaicheng","doi":"10.1109/ASICON.2009.5351181","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351181","url":null,"abstract":"In this study, design of a 16-bit, 400MSPS high-speed high-resolution current steering D/A converter is described. With pipelined thermometer decoding, multi-stage synchronous latch, current-source matching array design, two-stage active cascade design, and current switch nonlinear capacitor bootstrapping compensation technologies, DAC dynamic performances at high frequency are improved. The DAC uses the design in 0.25um CMOS process technology. Its die size is 4.84 mm × 4.9mm. High-frequency broadband SFDR>63dBc@Fout=(331/1024) × 400 MHz & Fsample =400MHz;","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123547169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A two-stage wake-up circuit for semi-passive RFID tag 半无源RFID标签的两级唤醒电路
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351345
Wei Chen, Wenyi Che, Xiao Wang, Chenling Huang, N. Yan, Hao Min, Jie Tan
{"title":"A two-stage wake-up circuit for semi-passive RFID tag","authors":"Wei Chen, Wenyi Che, Xiao Wang, Chenling Huang, N. Yan, Hao Min, Jie Tan","doi":"10.1109/ASICON.2009.5351345","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351345","url":null,"abstract":"A two-stage wake-up circuit for semi-passive Radio Frequency Identification (RFID) tag is designed and implemented in SMIC 0. 18 µm CMOS technology. In order to prolong the tag's battery life, a novel two-stage wake-up strategy with self-calibration is proposed. Measurement results show that the wake-up circuit has no static power and is free of Process, Voltage and Temperature (PVT) variations.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"226 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123719331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
A double-scroll based true random number generator with power and throughput adjustable 一个基于双卷轴的真随机数发生器，功率和吞吐量可调
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351446
Fuqiang Cao, Shuguo Li
{"title":"A double-scroll based true random number generator with power and throughput adjustable","authors":"Fuqiang Cao, Shuguo Li","doi":"10.1109/ASICON.2009.5351446","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351446","url":null,"abstract":"A new double-scroll chaotic oscillator circuit is proposed to design a true random number generator (TRNG) in CMOS process. The proposed oscillator is base on differential amplifiers by only MOS transistors and especially suitable to be integrated in standard logic process. The power of the oscillator is adjustable from 369µW to 2.7µW with different speed levels, proving low power operation ability and wide adjusting range. A low cost TRNG is realized and the quality of the output sequences is evaluated when the whole circuit consumes 53µW. The sequences pass the NIST FIPS140-1 standard randomness test at 1MHz clock frequency, showing better throughput-power efficiency compared to other papers1.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122652995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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