发布求助
文献互助 智能选刊 最新文献

2009 IEEE 8th International Conference on ASIC最新文献

筛选
英文 中文
Hierarchical SoC testing scheduling based on the ant colony algorithm 基于蚁群算法的SoC分级测试调度
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351198
Xiaole Cui, Wei Cheng, Xiaoye Wang, Liang Yin, Yachun Sun, Yan Zhou
{"title":"Hierarchical SoC testing scheduling based on the ant colony algorithm","authors":"Xiaole Cui, Wei Cheng, Xiaoye Wang, Liang Yin, Yachun Sun, Yan Zhou","doi":"10.1109/ASICON.2009.5351198","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351198","url":null,"abstract":"SoC testing scheduling is an NP hard problem, and it is more complex for the hierarchical SoC architecture. By formulating the SoC testing scheduling problem as a 2-D bin-packing model, this paper solves the problem for the hierarchical SoC with the Ant Colony Optimization (ACO) algorithm to reduce testing application time. Experimental results on ITC'02 benchmark circuits show that the ACO algorithm is more effective than earlier proposed methods.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122772022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A sub-1V 115nA 0.35µm CMOS voltage reference for ultra low-power applications 超低功耗应用的sub-1V 115nA 0.35µm CMOS基准电压
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351397
Haifeng Ma, F. Zhou
{"title":"A sub-1V 115nA 0.35µm CMOS voltage reference for ultra low-power applications","authors":"Haifeng Ma, F. Zhou","doi":"10.1109/ASICON.2009.5351397","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351397","url":null,"abstract":"A voltage reference circuit capable of sub-1V operation and with ultra-low power consumption is introduced in this paper. In the proposed circuit, proportional-to-absolute-temperature voltage is generated by using the series-connection of two NMOS devices working in sub-threshold region and the gate-to-source voltage of another NMOS device is adopted to realize the complementary-to-absolute-temperature voltage. Moreover, the temperature compensation is performed by using a switch-capacitor circuit. The proposed circuit is implemented in Chartered 0.35µm CMOS technology and occupies an active chip area of 0.021mm2. Post-layout simulation results show that it can operate with a supply voltage down to 0.9V while consuming 115nA ground current. With 1V power supply, the output voltage is 142.8mV at 25 °C and the temperature coefficient is 25.5ppm/°C1.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114505013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Design of a noise-canceling differential CMOS LNA for 3.1–10.6 GHz UWB receivers 3.1-10.6 GHz UWB接收机降噪差分CMOS LNA设计
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351170
Jinhua Liu, Guican Chen, Ruizhi Zhang
{"title":"Design of a noise-canceling differential CMOS LNA for 3.1–10.6 GHz UWB receivers","authors":"Jinhua Liu, Guican Chen, Ruizhi Zhang","doi":"10.1109/ASICON.2009.5351170","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351170","url":null,"abstract":"An ultra-wideband (UWB) 3.1–10.6 GHz fully differential low noise amplifier (LNA) employing the broadband noise-canceling technique is presented. With the proposed circuit topology, the noise from the input matching transistor is entirely suppressed over the full UWB band. The LNA is designed in 0.18µm CMOS technology. The simulated results show that the noise figure is 3.7–4.5 dB and the power gain is 13.4–14.1 dB in the desired UWB band, both the input and output reflection coefficients are below −10dB, and the IIP3 is −6.3dBm at 5.7 GHz. It consumes 12.5 mW from a 1.8V supply.1","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117043065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Stochastic inductance model of OTA-based inductor 基于ota的随机电感模型
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351186
R. Banchuin, Rougsan Chaisrichatorn, B. Chipipop
{"title":"Stochastic inductance model of OTA-based inductor","authors":"R. Banchuin, Rougsan Chaisrichatorn, B. Chipipop","doi":"10.1109/ASICON.2009.5351186","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351186","url":null,"abstract":"In this research, the effect of the stochastic nature of the bias current to the inductance of the OTA-based inductor has been explored and modeled as the corresponding Probability Density Function, PDF which the complete probabilistic distribution information can be obtained. This research has been performed based upon CMOS technology. The derived model has been found to provide a sufficient accuracy due to the strong agreement between its corresponding calculated Cumulative Distribution Function, CDF and the measured one. The proposed model is promisingly applicable to the OTA-based inductor of any topologies constructed with any basis OTA. Hence, it has been found to be a convenience tool for the design of various applications of the OTA-based inductor. Furthermore, the conceptual idea behind this research is also applicable to any current controlled active inductor.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129585015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Development and production of ZCS soft switching converter-based gate driver IC 基于ZCS软开关变换器的栅极驱动IC的开发与生产
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351405
Jun Jiang, Xian Wu, Bo Hu, J. Liao, Lu Zhao
{"title":"Development and production of ZCS soft switching converter-based gate driver IC","authors":"Jun Jiang, Xian Wu, Bo Hu, J. Liao, Lu Zhao","doi":"10.1109/ASICON.2009.5351405","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351405","url":null,"abstract":"In this paper, design of ZCS soft switching converter-based gate driver monolithic integrated circuit (IC) is presented. The circuit is developed in B6035 high-voltage bipolar process technology of Sichuan Institute of Solid-state Circuit. It consists of voltage detection logic, switch driving, isolation transformer excitation voltage blow-down unit circuits. The circuit and the isolation driving transformer jointly comprise the driving circuit of power MOS transistor. The principle of ZCS switching resonance is used to design the circuit. The circuit can drive MOS transistor with low power efficiently, and is especially suitable for the driving circuit of high-power ZCS soft-switching power supply.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129916301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A single channel 2GS/s 6-bit ADC with cascade resistive averaging 具有级联电阻平均的单通道2GS/s 6位ADC
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351501
Youtao Zhang, Xiaopeng Li, Ao Liu, Ming Zhang, Feng Qian
{"title":"A single channel 2GS/s 6-bit ADC with cascade resistive averaging","authors":"Youtao Zhang, Xiaopeng Li, Ao Liu, Ming Zhang, Feng Qian","doi":"10.1109/ASICON.2009.5351501","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351501","url":null,"abstract":"A single channel 2GS/s 6-bit ADC with cascade resistive averaging is demonstrated in 0.18µm CMOS. The proposed power efficient crossing connection method of averaging resistors has less reference voltage consumed than convention with excellent offset averaging. The peak DNL and INL are measured as 0.26 LSB and 0.21 LSB, respectively. The SNDR and SFDR have achieved 34.2 and 37.5dB, respectively, with 1.22 MHz input signal and 2GS/s. The SNDR and SFDR maintain above 30 and 35dB, respectively, up to1000MHz input signal and 900MS/s. The proposed ADC, including onchip track-and-hold amplifiers and clock buffers, consumes 570 mW from a single 1.8V supply while operating at 2GS/s1.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128286519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Speedup analysis of data-parallel applications on Multi-core NoCs 多核noc上数据并行应用的加速分析
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351597
Xiaowen Chen, Zhonghai Lu, A. Jantsch, Shuming Chen
{"title":"Speedup analysis of data-parallel applications on Multi-core NoCs","authors":"Xiaowen Chen, Zhonghai Lu, A. Jantsch, Shuming Chen","doi":"10.1109/ASICON.2009.5351597","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351597","url":null,"abstract":"As more computing cores are integrated onto a single chip, the effect of network communication latency is becoming more and more significant on Multi-core Network-on-Chips (NoCs). For data-parallel applications, we study the model of parallel speedup by including network communication latency in Amdahl's law. The speedup analysis considers the effect of network topology, network size, traffic model and computation/communication ratio. We also study the speedup efficiency. In our Multi-core NoC platform, a real data-parallel application, i.e. matrix multiplication, is used to validate the analysis. Our theoretical analysis and the application results show that the speedup improvement is nonlinear and the speedup efficiency decreases as the system size is scaled up. Such analysis can be used to guide architects and programmers to improve parallel processing efficiency by reducing network latency with optimized network design and increasing computation proportion in the program.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128936025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Thermal via planning aware force-directed floorplanning for D ICs 热通过规划意识力导向的平面规划为集成电路
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351314
Yun Huang, Qiang Zhou, Yici Cai
{"title":"Thermal via planning aware force-directed floorplanning for D ICs","authors":"Yun Huang, Qiang Zhou, Yici Cai","doi":"10.1109/ASICON.2009.5351314","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351314","url":null,"abstract":"The three-dimensional (3D) integration circuit is a new technology with higher integration density and better performance than 2D ICs. To solve the critical thermal issue in 3D layout, we propose a force-directed floorplanning algorithm. This algorithm naturally integrates with the planning of thermal vias and reasonably allocates white space for inserting the thermal vias. It solves the problem of the thermal distribution disturbance by the white space reassignment. Compare with the after-floorplanning thermal via planning algorithm, this algorithm decreases the number of thermal vias by 8.2% while increases the area by 3.5% on average.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130385620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design and Simulation of a SAW Filter and a new approach for bandwidth's tuning 声波滤波器的设计与仿真及一种新的带宽调谐方法
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351328
M. Sadeghi, R. Ghayour, H. Abiri, M. Karimi
{"title":"Design and Simulation of a SAW Filter and a new approach for bandwidth's tuning","authors":"M. Sadeghi, R. Ghayour, H. Abiri, M. Karimi","doi":"10.1109/ASICON.2009.5351328","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351328","url":null,"abstract":"In this paper the analysis and structure of the SAW devices including SAW filters are examined and improved. The SAW devices have good stability and reliability and they are widely used in high-frequency communication systems such as mobile and TV sets. The design procedure of band-pass SAW filter is explained and accordingly a band-pass SAW filter with center frequency of 100 MHz is designed and simulated by COMSOL MULTIPHYSISC and MATLAB soft ware. The idea of adding a sensitive layer between the input and out inter digital transducers (IDT) is also examined. It is shown that by changing the dimension of this layer, the specification of the filter is changed. Hence, it can be used as an effective tool for adjusting the desired specification of the filter such as the bandwidth and insertion loss.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123845337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Low-area 1-kb multi-bit OTP IP design 低区域1kb多比特OTP IP设计
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351324
Liyan Jin, Tae-Hoon Kim, Cheon-Hyo Lee, P. Ha, Young-Hee Kim
{"title":"Low-area 1-kb multi-bit OTP IP design","authors":"Liyan Jin, Tae-Hoon Kim, Cheon-Hyo Lee, P. Ha, Young-Hee Kim","doi":"10.1109/ASICON.2009.5351324","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351324","url":null,"abstract":"In this paper 1-kb multi-bit OTP IP, which is non-volatile memory, is designed for a power management IC. A conventional multi-bit OTP cell uses isolated NMOS transistor, but the cell size is large in the BCD process. So, PMOS transistor is used instead of the isolated NMOS transistor as antifuse, and the cell size is minimized by optimizing the size of PMOS transistor. In addition, an ESD protection circuit is added to prevent the case that any cell is programmed by high voltage at ESD test. The 1kb OTP IP is designed using Dongbu's 0.18µm BCD process and the layout size of the IP is 160.490 × 506.255 µm 21.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123329842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信