Speedup analysis of data-parallel applications on Multi-core NoCs

Abstract

As more computing cores are integrated onto a single chip, the effect of network communication latency is becoming more and more significant on Multi-core Network-on-Chips (NoCs). For data-parallel applications, we study the model of parallel speedup by including network communication latency in Amdahl's law. The speedup analysis considers the effect of network topology, network size, traffic model and computation/communication ratio. We also study the speedup efficiency. In our Multi-core NoC platform, a real data-parallel application, i.e. matrix multiplication, is used to validate the analysis. Our theoretical analysis and the application results show that the speedup improvement is nonlinear and the speedup efficiency decreases as the system size is scaled up. Such analysis can be used to guide architects and programmers to improve parallel processing efficiency by reducing network latency with optimized network design and increasing computation proportion in the program.