Low-area 1-kb multi-bit OTP IP design

Abstract

In this paper 1-kb multi-bit OTP IP, which is non-volatile memory, is designed for a power management IC. A conventional multi-bit OTP cell uses isolated NMOS transistor, but the cell size is large in the BCD process. So, PMOS transistor is used instead of the isolated NMOS transistor as antifuse, and the cell size is minimized by optimizing the size of PMOS transistor. In addition, an ESD protection circuit is added to prevent the case that any cell is programmed by high voltage at ESD test. The 1kb OTP IP is designed using Dongbu's 0.18µm BCD process and the layout size of the IP is 160.490 × 506.255 µm 21.