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2009 IEEE 8th International Conference on ASIC最新文献

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Analysis and design of high power supply rejection LDO 高电源抑制LDO的分析与设计
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351438
Yali Shao, Yi Wang, Zhi-hua Ning, Lenian He
{"title":"Analysis and design of high power supply rejection LDO","authors":"Yali Shao, Yi Wang, Zhi-hua Ning, Lenian He","doi":"10.1109/ASICON.2009.5351438","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351438","url":null,"abstract":"The power supply rejection (PSR) based on closed-loop low-dropout regulator (LDO) is analyzed to achieve high PSR in LDO, and help the designer meet the PSR requirement when considering the other performances of LDO. Using small signal model of MOS transistor, Kirchhoff's current/voltage law, and the tool of Mathematica, the PSR with DC gain, poles, and zeros of power stage and six kinds of basic amplifiers in LDO is analyzed theoretically, and proved by the simulation of Cadence Spectre. By tabling the PSR of eight Error Amplifier (EA) composite structures of two stages, the best combination of NMOS differential input amplifier (N-DA) + PMOS input common source amplifier (P-CS) is proposed on account of DC PSR property. An LDO containing an EA of the best structure has been designed with TSMC standard 0.35 µm CMOS process. The measurement result of PSR is −75 dB @ 1 kHz. A novel guideline to improve PSR of LDO is proposed and it provides a fresh design idea. Measurement results are in agreement with the analysis also.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123234782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Single-inductor dual-output converter with dynamic power distribution 具有动态功率分配的单电感双输出变换器
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351385
Yueming Sun, Xiaobo Wu, Menglian Zhao
{"title":"Single-inductor dual-output converter with dynamic power distribution","authors":"Yueming Sun, Xiaobo Wu, Menglian Zhao","doi":"10.1109/ASICON.2009.5351385","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351385","url":null,"abstract":"A single-inductor dual-output switching converter was presented in this paper. This converter can be applied to solar-cell portable devices as battery power management system. Considering the limited power supplied by solar cells, two output channels, battery charging and power regulating, were designed for this converter. Controlled by it, the output electric energy could be dynamically distributed between two channels. The state-machine is used to decide the amount of energy delivered to each channel. The converter chip is designed in a 1.5µm BCD (Bipolar-CMOS-DMOS) technology. Simulation results showed that all main targets were well achieved1.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124797826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Area minimization of MPRM circuits MPRM电路的面积最小化
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351633
Hui Li, Pengjun Wang, Jing Dai
{"title":"Area minimization of MPRM circuits","authors":"Hui Li, Pengjun Wang, Jing Dai","doi":"10.1109/ASICON.2009.5351633","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351633","url":null,"abstract":"In the minimization of the Mix Polarity Reed-Muller expression (MPRM) circuits, MPRM with different polarities can be got directly from a given Sum-Of-Product expression (SOP). Based on Kronecker Functional Decision Diagrams (KFDDs), a Polarity Conversion Technique (PCT) is proposed. MPRM under a desired polarity is obtained using PCT algorithm, then an Exhaustive-search Technique based on Gray Code (ETGC) is developed. ETGC algorithm is used for deriving MPRM with all polarities. Some experiments are performed comparing with optimizing the Fixed Polarity Reed-Muller expression (FPRM). Simulation results show that the minimal MPRM is smaller than FPRM, the average area savings is 60.7%.1","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121398725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A 1-V 32-µW 13-bit CMOS Sigma-Delta A/D converter for biomedical applications 用于生物医学应用的1-V 32µW 13位CMOS Sigma-Delta A/D转换器
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351498
Kunalan s/o Muthusamy, T. Hui Teo, Y. Xu
{"title":"A 1-V 32-µW 13-bit CMOS Sigma-Delta A/D converter for biomedical applications","authors":"Kunalan s/o Muthusamy, T. Hui Teo, Y. Xu","doi":"10.1109/ASICON.2009.5351498","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351498","url":null,"abstract":"This paper describes a low power, low voltage Sigma-Delta Analog to Digital Converter which consists of a Sigma-Delta modulator (SDM) and a decimation digital filter. A power efficient class AB OP-AMP, derived from inverter-like amplifier circuit, is proposed and a modified digital filter structure is employed for low frequency operation. Designed in a 0.18-µm CMOS technology, the overall SD-ADC is able to achieve an ENOB of 13.4 bit, a dynamic range of 88.6 dB and a peak SNR of 82.7 dB. The total power consumption of the ADC is 32 µW.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122910801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Mixed optimization method in design of FC-2 FC-2设计中的混合优化方法
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351595
Jie Jin, Xiaoxin Cui, Dunshan Yu
{"title":"Mixed optimization method in design of FC-2","authors":"Jie Jin, Xiaoxin Cui, Dunshan Yu","doi":"10.1109/ASICON.2009.5351595","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351595","url":null,"abstract":"The mixed optimization method proposed in this paper combines analysis of multi-level protocols with extraction of single-level protocol flow chart to design the accelerating hardware to improve the performance of FC-2. We implement the accelerating hardware with 0.18 CMOS standard technology. Compared with the Frame Based design method, the proposed method can improve the performance by 4.5 times in normal communication and even more when encountering error sequences with the 2.8 times area of the Frame Based one.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126283178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Look-Up-Table Based Differential Logic to counteract DPA attacks 基于查找表的差分逻辑对抗DPA攻击
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351561
Daheng Yue, Y. Sun, Minxuan Zhang, Shaoqing Li, Yutong Dai
{"title":"A Look-Up-Table Based Differential Logic to counteract DPA attacks","authors":"Daheng Yue, Y. Sun, Minxuan Zhang, Shaoqing Li, Yutong Dai","doi":"10.1109/ASICON.2009.5351561","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351561","url":null,"abstract":"Dual-Rail Precharge (DRP) logic styles, such as Wave Dynamic Differential Logic (WDDL), have been proposed as a countermeasure against Differential Power Analysis (DPA) for years. Because of the constant transition rate, the correlation between power consumption and signal values is significantly reduced. However, leakage still occurs in these logic styles caused by the difference of signal delay time. In this paper, a novel Look-Up-Table (LUT) Based Differential Logic (LBDL) is presented. The transition time of LBDL gates are independent of input values, hence the power consumption of LBDL is constant though the signals have different delays. Experimental results indicate that LBDL eliminates most of the leakage, while the performance and area costs are similar to WDDL1.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126531965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Congestion-driven floorplanning based on two-stage optimization 基于两阶段优化的拥挤驱动平面规划
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351235
Fubing Mao, Yuchun Ma, N. Xu, Shenghua Liu, Yu Wang, Xianlong Hong
{"title":"Congestion-driven floorplanning based on two-stage optimization","authors":"Fubing Mao, Yuchun Ma, N. Xu, Shenghua Liu, Yu Wang, Xianlong Hong","doi":"10.1109/ASICON.2009.5351235","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351235","url":null,"abstract":"In current VLSI design, routing congestion becomes a critical issue with deep submicron design technology. In order to avoid the rip-up and reroute which is a time-consuming process after the placement stage, in this paper, we proposed a new two-stage floorplanning approach for congestion optimization. In our approach we use the method of probability-estimation which uses the extended bounding box to evaluate the routing of nets. We also take use of the strategy of cell perturb to eliminate the routing congestion. Further reduction in congestion is obtained by our algorithm which guided by congestion. We have tested our approach on the MCNC benchmark circuits. The experiments show that our algorithms is efficient, stable and can reduce congestion largely. Compared with the traditional congestion-driven floorplanning, our 2-stage approach can alleviate the congestion efficiently in much shorter time.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124966823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A scan chains combined-balance strategy for hierarchical SoC DFT 分层SoC DFT的扫描链组合平衡策略
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351321
Jinyi Zhang, Dong Zhang, Xiaodong Yang, Yi Yang
{"title":"A scan chains combined-balance strategy for hierarchical SoC DFT","authors":"Jinyi Zhang, Dong Zhang, Xiaodong Yang, Yi Yang","doi":"10.1109/ASICON.2009.5351321","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351321","url":null,"abstract":"Intellectual Property (IP) cores reused technology improves System-on-a-Chip (SoC) design productivity. However, with more IP cores embedded in the deeper levels, the hierarchical architecture of SoC becomes complex, which also makes the test difficult. A Scan Chains Combined-Balance (SCCB) strategy is proposed in this paper to reconfigure and balance the scan chains, which helps reduce test time and overhead. The SCCB strategy is different from the traditional test method, wherein the Test Access Mechanism (TAM) and Scheduling are established as a virtual flattened form. We take experiments to verify the SCCB strategy based on the ITC'02 benchmarks. The experimental results show that the SCCB strategy is effective1.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131328387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An ultra low power sigma-delta modulator for hearing aid with double-sampling 一种用于助听器双采样的超低功耗σ - δ调制器
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351366
Da Qi, Yuanwen Li, Long Cheng, Jun Xu, Fan Ye, Junyan Ren
{"title":"An ultra low power sigma-delta modulator for hearing aid with double-sampling","authors":"Da Qi, Yuanwen Li, Long Cheng, Jun Xu, Fan Ye, Junyan Ren","doi":"10.1109/ASICON.2009.5351366","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351366","url":null,"abstract":"A single-loop third-order switched-capacitor Sigma-Delta modulator for hearing aid application is presented. Double-Sampling is introduced to achieve a high performance with comparative low power consumption. The effect of capacitor mismatch is further discussed. To over come the switch-on problem under low-voltage, bootstrapping is adopted in this design. The modulator is implemented under SMIC0.13µm mix signal technology, the post simulation results indicates the modulator achieves 92-dB SNDR in 8 kHz signal bandwidth with an OSR of 128. The power consumption is 38uW under 1-V supply voltage and the chip core size is 0.25 mm2.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130191252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A parallel intra prediction architecture for H.264 video decoding H.264视频解码的并行帧内预测结构
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351558
Xi Wang, Xiaoxin Cui, Dunshan Yu
{"title":"A parallel intra prediction architecture for H.264 video decoding","authors":"Xi Wang, Xiaoxin Cui, Dunshan Yu","doi":"10.1109/ASICON.2009.5351558","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351558","url":null,"abstract":"In this paper, an efficient hardware architecture for real-time implementation of intra prediction algorithm used in H.264 video coding standard is adopted. The hardware design is based on a novel organization of the intra prediction equations. Compared with conventional architecture, intra predict efficiency is enhanced. The Verilog RTL is verified to work at 103 MHz in a Xilinx II FPGA1.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"339 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121606695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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