{"title":"FC-2设计中的混合优化方法","authors":"Jie Jin, Xiaoxin Cui, Dunshan Yu","doi":"10.1109/ASICON.2009.5351595","DOIUrl":null,"url":null,"abstract":"The mixed optimization method proposed in this paper combines analysis of multi-level protocols with extraction of single-level protocol flow chart to design the accelerating hardware to improve the performance of FC-2. We implement the accelerating hardware with 0.18 CMOS standard technology. Compared with the Frame Based design method, the proposed method can improve the performance by 4.5 times in normal communication and even more when encountering error sequences with the 2.8 times area of the Frame Based one.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"85 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Mixed optimization method in design of FC-2\",\"authors\":\"Jie Jin, Xiaoxin Cui, Dunshan Yu\",\"doi\":\"10.1109/ASICON.2009.5351595\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The mixed optimization method proposed in this paper combines analysis of multi-level protocols with extraction of single-level protocol flow chart to design the accelerating hardware to improve the performance of FC-2. We implement the accelerating hardware with 0.18 CMOS standard technology. Compared with the Frame Based design method, the proposed method can improve the performance by 4.5 times in normal communication and even more when encountering error sequences with the 2.8 times area of the Frame Based one.\",\"PeriodicalId\":446584,\"journal\":{\"name\":\"2009 IEEE 8th International Conference on ASIC\",\"volume\":\"85 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-12-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 IEEE 8th International Conference on ASIC\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASICON.2009.5351595\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 IEEE 8th International Conference on ASIC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASICON.2009.5351595","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The mixed optimization method proposed in this paper combines analysis of multi-level protocols with extraction of single-level protocol flow chart to design the accelerating hardware to improve the performance of FC-2. We implement the accelerating hardware with 0.18 CMOS standard technology. Compared with the Frame Based design method, the proposed method can improve the performance by 4.5 times in normal communication and even more when encountering error sequences with the 2.8 times area of the Frame Based one.
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