Analysis and design of high power supply rejection LDO

Abstract

The power supply rejection (PSR) based on closed-loop low-dropout regulator (LDO) is analyzed to achieve high PSR in LDO, and help the designer meet the PSR requirement when considering the other performances of LDO. Using small signal model of MOS transistor, Kirchhoff's current/voltage law, and the tool of Mathematica, the PSR with DC gain, poles, and zeros of power stage and six kinds of basic amplifiers in LDO is analyzed theoretically, and proved by the simulation of Cadence Spectre. By tabling the PSR of eight Error Amplifier (EA) composite structures of two stages, the best combination of NMOS differential input amplifier (N-DA) + PMOS input common source amplifier (P-CS) is proposed on account of DC PSR property. An LDO containing an EA of the best structure has been designed with TSMC standard 0.35 µm CMOS process. The measurement result of PSR is −75 dB @ 1 kHz. A novel guideline to improve PSR of LDO is proposed and it provides a fresh design idea. Measurement results are in agreement with the analysis also.