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引用次数: 9
摘要
分析了基于闭环低差稳压器(LDO)的电源抑制(PSR)，以实现LDO的高PSR，并帮助设计者在考虑LDO的其他性能时满足PSR要求。利用MOS晶体管的小信号模型、Kirchhoff电流/电压定律和Mathematica软件，对LDO中具有直流增益、极和功率级零的PSR和6种基本放大器进行了理论分析，并通过Cadence Spectre仿真进行了验证。通过列出8种两级误差放大器(EA)复合结构的PSR，考虑到NMOS差分输入放大器(N-DA) + PMOS输入共源放大器(P-CS)的直流PSR特性，提出了最佳组合。采用TSMC标准的0.35µm CMOS工艺设计了具有最佳结构EA的LDO。PSR的测量结果为- 75 dB @ 1 kHz。提出了一种提高LDO的PSR的新方法，为LDO的设计提供了新的思路。测量结果与分析结果一致。
Analysis and design of high power supply rejection LDO
The power supply rejection (PSR) based on closed-loop low-dropout regulator (LDO) is analyzed to achieve high PSR in LDO, and help the designer meet the PSR requirement when considering the other performances of LDO. Using small signal model of MOS transistor, Kirchhoff's current/voltage law, and the tool of Mathematica, the PSR with DC gain, poles, and zeros of power stage and six kinds of basic amplifiers in LDO is analyzed theoretically, and proved by the simulation of Cadence Spectre. By tabling the PSR of eight Error Amplifier (EA) composite structures of two stages, the best combination of NMOS differential input amplifier (N-DA) + PMOS input common source amplifier (P-CS) is proposed on account of DC PSR property. An LDO containing an EA of the best structure has been designed with TSMC standard 0.35 µm CMOS process. The measurement result of PSR is −75 dB @ 1 kHz. A novel guideline to improve PSR of LDO is proposed and it provides a fresh design idea. Measurement results are in agreement with the analysis also.
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