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2009 IEEE 8th International Conference on ASIC最新文献

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A sample/hold circuit for 80MSPS 14-bit A/D converter 用于80MSPS 14位A/D转换器的采样/保持电路
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351390
Xiao Kunguang, Wang Yuxing, Xu Minyuan, Zhu Chan
{"title":"A sample/hold circuit for 80MSPS 14-bit A/D converter","authors":"Xiao Kunguang, Wang Yuxing, Xu Minyuan, Zhu Chan","doi":"10.1109/ASICON.2009.5351390","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351390","url":null,"abstract":"In this paper, a sample/hold circuit for switched capacitor structure in 0.35um CMOS process technology is described. The sample/hold circuit is used for 14-bit pipelined A/D converter with a conversion rate up to 80MSPS. In the circuit, the differential unity gain structure is employed. The impact of channel injected charges is reduced through sequential control. The amplifier with a folded cascode gain intensified structure is adopted, so desired gain and bandwidth of the circuit are obtained. By circuit simulation, the maximum harmonic distortion of the sample/hold circuit at a supply voltage of 3V is −90dB at 80MSPS with input signal of 2Vpp. As a result, the DNL is 0.8/−0.9 LSB, the INL is 3.1/−3.7 LSB, the SNR is 70.2dB,and the SFDR is 89.3dB.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133914693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design and implementation of a security-enhanced baseband system for UHF RFID tag 超高频RFID标签安全增强基带系统的设计与实现
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351524
Qian Yongzhen, Wang Xin-an, Feng Xiao-xing, Gu Weqing
{"title":"Design and implementation of a security-enhanced baseband system for UHF RFID tag","authors":"Qian Yongzhen, Wang Xin-an, Feng Xiao-xing, Gu Weqing","doi":"10.1109/ASICON.2009.5351524","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351524","url":null,"abstract":"This paper presents a security-enhanced baseband system for UHF RFID tag, which is based on ISO18000-6B protocol. The proposed baseband system consists of the following modules: Receiver, Controller, Power Management (PM), Transmitter, Advanced Encryption Standard with 128 bits cryptographic key (AES-128), and Cyclic Redundancy Check (CRC). AES-128 is the encryption engine, which is designed and implemented properly for low cost requirement. Tag uses AES-128 to protect sensitive data in memory and realize mutual authentication with reader. As the actual length of data transacted between reader and tag is less than 128 bits, a novel data flow is given to enhance security strength. The chip was designed using 0.18µm CMOS process. Total area of the baseband system is 685µmX360µm excluding pads. Power analysis shows that it consumes 6.9µw@1V. The chip is under fabrication.1","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131889624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Design of a high reliable L1 data cache with redundant cache 具有冗余缓存的高可靠性L1数据缓存的设计
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351610
Zhaolin Li, Xinyue Zhang, Huiqing Luo
{"title":"Design of a high reliable L1 data cache with redundant cache","authors":"Zhaolin Li, Xinyue Zhang, Huiqing Luo","doi":"10.1109/ASICON.2009.5351610","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351610","url":null,"abstract":"Modern high-performance processors utilize cache memory systems to tolerate the increasing latency of main memory. Along with IC technology improvement, complicated cache memory systems in processors are very vulnerable to soft errors under severe environment. To deal with multiple soft errors with little impact on hardware overhead and performance, this paper proposes a new cache memory system, in which redundant cache blocks are integrated into a set-associative L1 data cache. Each redundant cache block is used to store the replica of each “dirty”data in correspondence with L1 data cache blocks. In order to realize the detection of multiple soft errors with little hardware overhead, a bit interleaving group parity code is adopted to detect multiple soft errors in L1 data cache blocks. Moreover, in order to increase the mapping rate between L1 data cache blocks and the redundant cache blocks, an early write-back based protocol is introduced, in which all dirty cache blocks are written back to L2 cache at the intervals of a determined cycle number. The proposed cache system can provide more powerful soft error protection than conventional error correction codes. Experiment results show that the cache system proposed in this paper can provide replicas for almost 100% of dirty cache blocks in L1 data cache on average1.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133778220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A low breakdown-voltage charge pump based on Cockcroft-Walton structure 基于Cockcroft-Walton结构的低击穿电压电荷泵
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351433
Renyuan Zhang, Zhangcai Huang, Y. Inoue
{"title":"A low breakdown-voltage charge pump based on Cockcroft-Walton structure","authors":"Renyuan Zhang, Zhangcai Huang, Y. Inoue","doi":"10.1109/ASICON.2009.5351433","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351433","url":null,"abstract":"A Cockcroft-Walton type charge pump circuit is proposed in this paper. Compared with Dickson type, each transistor and capacitor in the proposed circuit just stand against the voltage less than one Vdd, so that a low break-down voltage process can be applied to this kind of charge pump to reduce the chip area cost and break-down risk. By using the proposed structure, the performances of voltage boosting efficiency and power efficiency can reach 98.9% and 87%.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115708603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A synchronous boost regulator with PWM/PFM mode operation 具有PWM/PFM模式操作的同步升压调节器
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351401
W. Liou, Ping-Hsing Chen, Jiun-Chang Tzeng
{"title":"A synchronous boost regulator with PWM/PFM mode operation","authors":"W. Liou, Ping-Hsing Chen, Jiun-Chang Tzeng","doi":"10.1109/ASICON.2009.5351401","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351401","url":null,"abstract":"This paper presents a synchronous boost regulator with PWM/PFM mode of operation. It uses synchronous rectification architecture to reduce the conduction loss and improve the efficiency. Furthermore, this paper features a two-level soft-start circuit which prevents the presence of large current generation during system start-up. The simulation results show an efficiency of more than 90% with an input voltage range of 2.7V∼4.2V and with a load current of 1mA to 200mA. This regulator is suitable for ion-battery supply application. It uses TSMC's 0.35um 2P4M CMOS process1.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114235279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A 200MHz low-power direct digital frequency synthesizer based on mixed structure of angle rotation 基于角度旋转混合结构的200MHz低功耗直接数字频率合成器
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351174
W. Shuqin, Hua Yiding, Zang Kaihong, Yu Zongguang
{"title":"A 200MHz low-power direct digital frequency synthesizer based on mixed structure of angle rotation","authors":"W. Shuqin, Hua Yiding, Zang Kaihong, Yu Zongguang","doi":"10.1109/ASICON.2009.5351174","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351174","url":null,"abstract":"Direct digital frequency synthesizer(DDS) is a new technology for frequency synthesis. This paper describers the implementation of a direct digital frequency employs a new architecture in 0.35µm CMOS technology. The first rotation implementer by using a CORDIC realized in pipeline and carry-save arithmetic. The directions of the CORDIC rotations are computed in parallel by using a little lookup table, for the first rotation. In order to reduce the circuit latency and increase the speed, the final rotation is multiplier-based, employing CMOS-DPL logic. The final circuit experiment results show the power dissipation as low as 1.44mW/MHz and the maximum clock frequency 200 MHZ1","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114339214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Architectural integration of RSA accelerator into MIPS processor RSA加速器与MIPS处理器的架构集成
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351536
Shi-ting Lu, Suiyu Zhang, Yulong Zhang, Jun Han, Xiaoyang Zeng
{"title":"Architectural integration of RSA accelerator into MIPS processor","authors":"Shi-ting Lu, Suiyu Zhang, Yulong Zhang, Jun Han, Xiaoyang Zeng","doi":"10.1109/ASICON.2009.5351536","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351536","url":null,"abstract":"In the domain of information security, people are now prone to implement the cryptographic algorithm through hardware. Usually, these algorithms are designed as coprocessors and a system integrator must use some kind of protocol to correctly use it. This paper presents a convenient way to integrate RSA-engine onto MIPS processor based system by making use of the CP2 extension of MIPS architecture. A concrete implementation of RSA is given, and a dedicated hardware architecture is presented to integrate the MIPS processor and RSA accelerator. Also, software issues are raised and sample codes are given1.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"210 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114465733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
An 0.35μm/ CMOS 2.4Gb/s LVDS for high-speed DAC 用于高速DAC的0.35μm/ CMOS 2.4Gb/s LVDS
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351442
Xingfa Huang, L. Li, Kaikai Xu, Ruzhang Li, Cheng Shu
{"title":"An 0.35μm/ CMOS 2.4Gb/s LVDS for high-speed DAC","authors":"Xingfa Huang, L. Li, Kaikai Xu, Ruzhang Li, Cheng Shu","doi":"10.1109/ASICON.2009.5351442","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351442","url":null,"abstract":"In the light of application to high-speed DAC, the design and achievement of a novel high-performance CMOS LVDS receiving circuits are described in this paper. By introduction of intrinsic offset, a fixed hysteresis voltage is obtained. The whole circuit doesn't need any local feedback, and the high-speed performance of the original circuit doesn't change with introduction of hysteresis voltage. Therefore the circuit has twofold advantages: a stable hysteresis voltage and a high-speed operation. The circuit was developed in Chartered 0.35μm CMOS process technology. The tested results showed that the circuit worked stably at an operational voltage of 3.3V at a transmission speed of 2.4Gb/s. The chip size of the circuit was 0.021mm2, and the power consumption of the circuit was 8mW1.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116187616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A low power high date rate ASK IF receiver 一种低功耗、高数据速率的中频请求接收机
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351621
Xiaoman Wang, B. Chi, Zhihua Wang
{"title":"A low power high date rate ASK IF receiver","authors":"Xiaoman Wang, B. Chi, Zhihua Wang","doi":"10.1109/ASICON.2009.5351621","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351621","url":null,"abstract":"A low power high data rate ASK IF receiver is proposed. It consists of one digital-control AGC loop and an ASK detector. By utilizing the scrambler concept in the digital communication systems, the gain of PGA in the AGC loop is adjusted discretely by a gain control block to eliminate the multi-digit A/D converter. The ASK IF receiver has been implemented in 0.18µm CMOS and the overall power consumption is 2.175mW with a supply voltage of 1.8V. The operating frequency is 10M, and the data rate is 2Mbps. The amplitude of detectable input signal can range from 5µV to 900mV1.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"52 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115277655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Output test compression for compound defect diagnosis 用于复合缺陷诊断的输出测试压缩
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351349
Chao-Wen Tzeng, Shi-Yu Huang
{"title":"Output test compression for compound defect diagnosis","authors":"Chao-Wen Tzeng, Shi-Yu Huang","doi":"10.1109/ASICON.2009.5351349","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351349","url":null,"abstract":"In modern scan architecture, it is often desired to compact the output response without jeopardizing the diagnostic resolution. In this work, we propose an output masking scheme to meet such a stringent requirement. We consider a practical scenario in which an output compactor is in use. We aim to support the harshest condition called compound defect diagnosis, in which faults exist in both the scan chain and the core logic. To overcome the loss of the diagnostic resolution, we incorporate a split-masking scheme, by which one can easily separate the output responses of the faulty chains from those of the fault-free ones. The experimental results demonstrate that the proposed scheme can recover the diagnostic resolution loss induced by an output compactor almost completely without sacrificing the compaction ratio1.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115294887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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