{"title":"基于角度旋转混合结构的200MHz低功耗直接数字频率合成器","authors":"W. Shuqin, Hua Yiding, Zang Kaihong, Yu Zongguang","doi":"10.1109/ASICON.2009.5351174","DOIUrl":null,"url":null,"abstract":"Direct digital frequency synthesizer(DDS) is a new technology for frequency synthesis. This paper describers the implementation of a direct digital frequency employs a new architecture in 0.35µm CMOS technology. The first rotation implementer by using a CORDIC realized in pipeline and carry-save arithmetic. The directions of the CORDIC rotations are computed in parallel by using a little lookup table, for the first rotation. In order to reduce the circuit latency and increase the speed, the final rotation is multiplier-based, employing CMOS-DPL logic. The final circuit experiment results show the power dissipation as low as 1.44mW/MHz and the maximum clock frequency 200 MHZ1","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"20 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"A 200MHz low-power direct digital frequency synthesizer based on mixed structure of angle rotation\",\"authors\":\"W. Shuqin, Hua Yiding, Zang Kaihong, Yu Zongguang\",\"doi\":\"10.1109/ASICON.2009.5351174\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Direct digital frequency synthesizer(DDS) is a new technology for frequency synthesis. This paper describers the implementation of a direct digital frequency employs a new architecture in 0.35µm CMOS technology. The first rotation implementer by using a CORDIC realized in pipeline and carry-save arithmetic. The directions of the CORDIC rotations are computed in parallel by using a little lookup table, for the first rotation. In order to reduce the circuit latency and increase the speed, the final rotation is multiplier-based, employing CMOS-DPL logic. The final circuit experiment results show the power dissipation as low as 1.44mW/MHz and the maximum clock frequency 200 MHZ1\",\"PeriodicalId\":446584,\"journal\":{\"name\":\"2009 IEEE 8th International Conference on ASIC\",\"volume\":\"20 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-12-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 IEEE 8th International Conference on ASIC\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASICON.2009.5351174\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 IEEE 8th International Conference on ASIC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASICON.2009.5351174","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 200MHz low-power direct digital frequency synthesizer based on mixed structure of angle rotation
Direct digital frequency synthesizer(DDS) is a new technology for frequency synthesis. This paper describers the implementation of a direct digital frequency employs a new architecture in 0.35µm CMOS technology. The first rotation implementer by using a CORDIC realized in pipeline and carry-save arithmetic. The directions of the CORDIC rotations are computed in parallel by using a little lookup table, for the first rotation. In order to reduce the circuit latency and increase the speed, the final rotation is multiplier-based, employing CMOS-DPL logic. The final circuit experiment results show the power dissipation as low as 1.44mW/MHz and the maximum clock frequency 200 MHZ1
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