{"title":"一种低功耗、高数据速率的中频请求接收机","authors":"Xiaoman Wang, B. Chi, Zhihua Wang","doi":"10.1109/ASICON.2009.5351621","DOIUrl":null,"url":null,"abstract":"A low power high data rate ASK IF receiver is proposed. It consists of one digital-control AGC loop and an ASK detector. By utilizing the scrambler concept in the digital communication systems, the gain of PGA in the AGC loop is adjusted discretely by a gain control block to eliminate the multi-digit A/D converter. The ASK IF receiver has been implemented in 0.18µm CMOS and the overall power consumption is 2.175mW with a supply voltage of 1.8V. The operating frequency is 10M, and the data rate is 2Mbps. The amplitude of detectable input signal can range from 5µV to 900mV1.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"52 2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A low power high date rate ASK IF receiver\",\"authors\":\"Xiaoman Wang, B. Chi, Zhihua Wang\",\"doi\":\"10.1109/ASICON.2009.5351621\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A low power high data rate ASK IF receiver is proposed. It consists of one digital-control AGC loop and an ASK detector. By utilizing the scrambler concept in the digital communication systems, the gain of PGA in the AGC loop is adjusted discretely by a gain control block to eliminate the multi-digit A/D converter. The ASK IF receiver has been implemented in 0.18µm CMOS and the overall power consumption is 2.175mW with a supply voltage of 1.8V. The operating frequency is 10M, and the data rate is 2Mbps. The amplitude of detectable input signal can range from 5µV to 900mV1.\",\"PeriodicalId\":446584,\"journal\":{\"name\":\"2009 IEEE 8th International Conference on ASIC\",\"volume\":\"52 2 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-12-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 IEEE 8th International Conference on ASIC\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASICON.2009.5351621\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 IEEE 8th International Conference on ASIC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASICON.2009.5351621","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A low power high data rate ASK IF receiver is proposed. It consists of one digital-control AGC loop and an ASK detector. By utilizing the scrambler concept in the digital communication systems, the gain of PGA in the AGC loop is adjusted discretely by a gain control block to eliminate the multi-digit A/D converter. The ASK IF receiver has been implemented in 0.18µm CMOS and the overall power consumption is 2.175mW with a supply voltage of 1.8V. The operating frequency is 10M, and the data rate is 2Mbps. The amplitude of detectable input signal can range from 5µV to 900mV1.
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