{"title":"用于80MSPS 14位A/D转换器的采样/保持电路","authors":"Xiao Kunguang, Wang Yuxing, Xu Minyuan, Zhu Chan","doi":"10.1109/ASICON.2009.5351390","DOIUrl":null,"url":null,"abstract":"In this paper, a sample/hold circuit for switched capacitor structure in 0.35um CMOS process technology is described. The sample/hold circuit is used for 14-bit pipelined A/D converter with a conversion rate up to 80MSPS. In the circuit, the differential unity gain structure is employed. The impact of channel injected charges is reduced through sequential control. The amplifier with a folded cascode gain intensified structure is adopted, so desired gain and bandwidth of the circuit are obtained. By circuit simulation, the maximum harmonic distortion of the sample/hold circuit at a supply voltage of 3V is −90dB at 80MSPS with input signal of 2Vpp. As a result, the DNL is 0.8/−0.9 LSB, the INL is 3.1/−3.7 LSB, the SNR is 70.2dB,and the SFDR is 89.3dB.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A sample/hold circuit for 80MSPS 14-bit A/D converter\",\"authors\":\"Xiao Kunguang, Wang Yuxing, Xu Minyuan, Zhu Chan\",\"doi\":\"10.1109/ASICON.2009.5351390\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, a sample/hold circuit for switched capacitor structure in 0.35um CMOS process technology is described. The sample/hold circuit is used for 14-bit pipelined A/D converter with a conversion rate up to 80MSPS. In the circuit, the differential unity gain structure is employed. The impact of channel injected charges is reduced through sequential control. The amplifier with a folded cascode gain intensified structure is adopted, so desired gain and bandwidth of the circuit are obtained. By circuit simulation, the maximum harmonic distortion of the sample/hold circuit at a supply voltage of 3V is −90dB at 80MSPS with input signal of 2Vpp. As a result, the DNL is 0.8/−0.9 LSB, the INL is 3.1/−3.7 LSB, the SNR is 70.2dB,and the SFDR is 89.3dB.\",\"PeriodicalId\":446584,\"journal\":{\"name\":\"2009 IEEE 8th International Conference on ASIC\",\"volume\":\"9 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-12-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 IEEE 8th International Conference on ASIC\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASICON.2009.5351390\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 IEEE 8th International Conference on ASIC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASICON.2009.5351390","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A sample/hold circuit for 80MSPS 14-bit A/D converter
In this paper, a sample/hold circuit for switched capacitor structure in 0.35um CMOS process technology is described. The sample/hold circuit is used for 14-bit pipelined A/D converter with a conversion rate up to 80MSPS. In the circuit, the differential unity gain structure is employed. The impact of channel injected charges is reduced through sequential control. The amplifier with a folded cascode gain intensified structure is adopted, so desired gain and bandwidth of the circuit are obtained. By circuit simulation, the maximum harmonic distortion of the sample/hold circuit at a supply voltage of 3V is −90dB at 80MSPS with input signal of 2Vpp. As a result, the DNL is 0.8/−0.9 LSB, the INL is 3.1/−3.7 LSB, the SNR is 70.2dB,and the SFDR is 89.3dB.
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