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2009 IEEE 8th International Conference on ASIC最新文献

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A low noise class-AB amplifier for voice communication 用于语音通信的低噪声ab类放大器
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351478
Jiang Yu, Jiang Shi
{"title":"A low noise class-AB amplifier for voice communication","authors":"Jiang Yu, Jiang Shi","doi":"10.1109/ASICON.2009.5351478","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351478","url":null,"abstract":"Class AB amplifier is widely used as analog building blocks for many applications. The recent development of class AB amp for low power and low voltage applications is reviewed and summarized. A low noise design realization is fabricated in 0.35 um CMOS technology. For 10pF cap load, it shows GBW of 800KHz with supply voltage of 2.5V and about 5uA quiescent current.1","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"276 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122659470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 1.5 GHz linear-in-dB Variable Gain Amplifier with process and temperature tracking in 0.18-µm CMOS 一种采用0.18µm CMOS工艺和温度跟踪的1.5 GHz线性db可变增益放大器
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351465
Xiong Liu, A. Willson
{"title":"A 1.5 GHz linear-in-dB Variable Gain Amplifier with process and temperature tracking in 0.18-µm CMOS","authors":"Xiong Liu, A. Willson","doi":"10.1109/ASICON.2009.5351465","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351465","url":null,"abstract":"A linear-in-dB CMOS Variable Gain Amplifier (VGA) targeting large-bandwidth applications, such as a DVD front-end and a Digital TV tuner's RF VGA is implemented in 0.18-µm CMOS. With a novel process and temperature variation tracking scheme and a charge-pump based negative supply to extend tracking range and improve linearity, this VGA provides stable −6 to 16 dB amplification across PVT variations. With less than 3 mA biasing current, the 3-dB bandwidth is more than 1.5 GHz and the THD is less than −45 dB for output swings greater than 500 mVppd.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122664290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Battery-less piezoceramics mode energy harvesting for automobile TPMS 汽车TPMS的无电池压电陶瓷模式能量收集
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351190
Liji Wu, Yixiang Wang, Chen Jia, Chun Zhang
{"title":"Battery-less piezoceramics mode energy harvesting for automobile TPMS","authors":"Liji Wu, Yixiang Wang, Chen Jia, Chun Zhang","doi":"10.1109/ASICON.2009.5351190","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351190","url":null,"abstract":"A battery-less Tire Pressure Monitoring System (TPMS) with piezoceramics mode energy harvesting is presented. A chip of power recovery circuit at piezoceramics mode is designed and implemented at Chartered 0.35µm High Voltage CMOS Process. Based on testing results, with the piezoceramics, the chip converts mechanical strain energy to DC power which provides stable voltage output around 3V, and about 10mA current for almost 20ms at recurring working mode for sensor, MCU and data transmitter to work well in a tire monitoring module of TPMS. And taking the frequency multiplication method mentioned last, the application of this type of battery-less TPMS in real car environment is hopeful1.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122758984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
Verilog-A based implementation for coupled model of single event transients in look-up table technique 基于Verilog-A的单事件瞬态耦合模型在查表技术中的实现
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351334
Zhao Xueqian, Zhao Zhenyu, Zhang Minxuan, Li Shaoqing
{"title":"Verilog-A based implementation for coupled model of single event transients in look-up table technique","authors":"Zhao Xueqian, Zhao Zhenyu, Zhang Minxuan, Li Shaoqing","doi":"10.1109/ASICON.2009.5351334","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351334","url":null,"abstract":"A Verilog-A based implementation of voltage coupled model is developed for Single-Event Transients (SETs) in microelectronic circuits. By implementing a look-up table in Verilog-A, the SET current source performs well and consents with the results from Technology CAD (TCAD) based mix-mode simulation. Simulation results from Synopsys Hspice 2008 indicates that the method proposed in this paper correctly reveals the current “tail” which reflects the equilibrium course of charge collection. Moreover, the Verilog-A based method speeds up the simulation by over 18,000 times than the mix-mode simulation and is also faster than the piecewise linear source (PWL). Furthermore, this Verilog-A based LUT method cooperates with the design flow well and can be easily applied to various applications with wide supports of industrial EDA tools1.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131383229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An improved edge-adaptive image scaling algorithm 一种改进的边缘自适应图像缩放算法
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351551
W. Jiang, Haifeng Xu, Gengsheng Chen, Wenqing Zhao, W. Xu
{"title":"An improved edge-adaptive image scaling algorithm","authors":"W. Jiang, Haifeng Xu, Gengsheng Chen, Wenqing Zhao, W. Xu","doi":"10.1109/ASICON.2009.5351551","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351551","url":null,"abstract":"Image scaling is an important part of image processing. In order to protect edge characteristics of images, this paper proposes an improved edge-adaptive image scaling algorithm, in which the image is mainly divided into four kinds of image blocks with simple directional edge detector, and interpolation is then adaptively carried out along edge direction. Our experiment shows that the proposed algorithm can produce high-quality images with well-preserved edge and low computational complexity.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131545258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A highly efficient inverse transform architecture for multi-standard HDTV decoder 一种适用于多标准HDTV解码器的高效逆变换结构
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351634
Hang Zhang, Peilin Liu, Yu Hong, Dajiang Zhou, S. Goto
{"title":"A highly efficient inverse transform architecture for multi-standard HDTV decoder","authors":"Hang Zhang, Peilin Liu, Yu Hong, Dajiang Zhou, S. Goto","doi":"10.1109/ASICON.2009.5351634","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351634","url":null,"abstract":"This paper presents a VLSI implementation for inverse transforms of H.264/AVC, AVS and MPEG1/2/4. Based on distributed arithmetic, the inverse transforms of the three video coding standards share the unique architecture, which achieves less hardware cost and better decoding efficiency than separate designs. The core element of the distributed arithmetic is implemented with pipelined architecture, where only table accessing, shift and accumulation are needed. To optimize the efficiency of inverse transformation, a zero pre-detecting scheme is used in the proposed architecture. The distributed arithmetic tables are organized as differential code to reduce almost half of the ROM size. With our dedicated modularization, the proposed architecture is suitable for multi-standard HDTV applications.1","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"126 22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128024325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
True single-phase energy recovery flip-flop for low-power application 低功耗应用的真正单相能量恢复触发器
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351173
L. Gao, Yumei Zhou, Hainan Liu
{"title":"True single-phase energy recovery flip-flop for low-power application","authors":"L. Gao, Yumei Zhou, Hainan Liu","doi":"10.1109/ASICON.2009.5351173","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351173","url":null,"abstract":"In this paper, we present a true single-phase energy recovery flip-flop, which can cascade with conventional combinational logic circuits. Compared with the conventional flip-flop, the true single-phase energy recovery flip-flop exhibits a power reduction of up to 31% at frequency of 200MHz and operating voltages of 1.2V in 0.18µm process. In order to validate the function of energy recovery flip-flop, a chip was designed with 0.18µm process1.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"486 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132751918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A new layout method to improve the thermal stability of Multi-finger power HBT 一种提高多指功率HBT热稳定性的新型布局方法
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351430
Y. Chen, H. Shen, X. Liu
{"title":"A new layout method to improve the thermal stability of Multi-finger power HBT","authors":"Y. Chen, H. Shen, X. Liu","doi":"10.1109/ASICON.2009.5351430","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351430","url":null,"abstract":"A new layout method to improve the thermal stability of Multi-finger Power heterojunction bipolar transistors(HBT) is presented in this paper. In the new layout the through-wafer-via is inserted into the central of the Multi-finger Power HBT and the emitter fingers were connected by a wide metal layer that was exactly on the active thermal emitter area. According to the experimental results of a 8 fingers GaAs power HBT, the new layout method with compare to the routine layout method can reduce the thermal resistance from 242°C/W to 163°C/W and expand the thermal stability power density from 0.76 mW/µ m2 to 1.14 mW/µ m2. And also the radio frequency( RF) gain loss of the power HBT due to the thermal effect was suppressed with the improvement of the thermal stability. 1","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133675944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Design of on-chip image processing based on APB bus with CMOS image sensor 基于APB总线和CMOS图像传感器的片上图像处理设计
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351535
Ge Zhiwei, Yao Su-ying, Xu Jiangtao
{"title":"Design of on-chip image processing based on APB bus with CMOS image sensor","authors":"Ge Zhiwei, Yao Su-ying, Xu Jiangtao","doi":"10.1109/ASICON.2009.5351535","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351535","url":null,"abstract":"This paper presents a novel on-chip image processing architecture with CMOS image sensor, which applies APB bus to implement image processing. The proposed architecture presents the issues related to color image processing and gives the differences between the proposed architecture and the traditional image processing pipeline used in digital still cameras. Considering the hardware implementation and power requirement, this paper combines two efficient auto white balance method together to adjust the three independent color channels. By applied on FPGA, the proposed method can greatly enhance the image quality of raw data. The results show that the proposed image processing architecture and the auto white balance algorithms work well on FPGA development board.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133709116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A spread spectrum clock generator with phase-rotation algorithm for 6Gbps clock and data recovery 采用相位旋转算法的扩频时钟发生器，可实现6Gbps时钟和数据恢复
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351414
Chih-Hsien Lin, Yen-Ying Huang, Shu-Rung Li, Yuan-Pu Cheng, S. Jou
{"title":"A spread spectrum clock generator with phase-rotation algorithm for 6Gbps clock and data recovery","authors":"Chih-Hsien Lin, Yen-Ying Huang, Shu-Rung Li, Yuan-Pu Cheng, S. Jou","doi":"10.1109/ASICON.2009.5351414","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351414","url":null,"abstract":"A low jitter phase-lock-loop (PLL) and a proposed spread-spectrum clock method for Serial ATA with phase rotation is presented. The low jitter PLL uses error amplifier to resolve the current mismatch in charge pump and the 3rd order loop filter is adopted to reduce the reference spur. A passive resistance is presented in our design to reduce the KVCO. Our spread spectrum clock generator (SSCG) for Serial ATA specification is down spread 5000 ppm with a triangular waveform and the modulation frequency is 30∼33KHz. Spread-spectrum technique using PLL with a Δ Σ modulator and phase rotation algorithm is reported. The proposed circuit has been designed in a 90-nm CMOS process. The non-spread spectrum clocking has a peak to peak jitter of 512fs and consumes 5.87mW at 1.4GHz. The EMI reduction is about 19.24dB.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133709720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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