采用相位旋转算法的扩频时钟发生器,可实现6Gbps时钟和数据恢复

Chih-Hsien Lin, Yen-Ying Huang, Shu-Rung Li, Yuan-Pu Cheng, S. Jou
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引用次数: 0

摘要

提出了一种低抖动锁相环(PLL)和扩频时钟方法。低抖动锁相环采用误差放大器解决电荷泵中的电流失配问题,采用三阶环路滤波器减小参考杂散。在我们的设计中提出了一个被动电阻来降低KVCO。我们串行ATA规范的扩频时钟发生器(SSCG)向下扩展5000 ppm,具有三角形波形,调制频率为30 ~ 33KHz。介绍了一种采用Δ Σ调制器和相位旋转算法的锁相环扩频技术。该电路采用90纳米CMOS工艺设计。非扩频时钟的峰值抖动为512fs,在1.4GHz时消耗5.87mW。EMI降低约19.24dB。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A spread spectrum clock generator with phase-rotation algorithm for 6Gbps clock and data recovery
A low jitter phase-lock-loop (PLL) and a proposed spread-spectrum clock method for Serial ATA with phase rotation is presented. The low jitter PLL uses error amplifier to resolve the current mismatch in charge pump and the 3rd order loop filter is adopted to reduce the reference spur. A passive resistance is presented in our design to reduce the KVCO. Our spread spectrum clock generator (SSCG) for Serial ATA specification is down spread 5000 ppm with a triangular waveform and the modulation frequency is 30∼33KHz. Spread-spectrum technique using PLL with a Δ Σ modulator and phase rotation algorithm is reported. The proposed circuit has been designed in a 90-nm CMOS process. The non-spread spectrum clocking has a peak to peak jitter of 512fs and consumes 5.87mW at 1.4GHz. The EMI reduction is about 19.24dB.
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