A highly efficient inverse transform architecture for multi-standard HDTV decoder

This paper presents a VLSI implementation for inverse transforms of H.264/AVC, AVS and MPEG1/2/4. Based on distributed arithmetic, the inverse transforms of the three video coding standards share the unique architecture, which achieves less hardware cost and better decoding efficiency than separate designs. The core element of the distributed arithmetic is implemented with pipelined architecture, where only table accessing, shift and accumulation are needed. To optimize the efficiency of inverse transformation, a zero pre-detecting scheme is used in the proposed architecture. The distributed arithmetic tables are organized as differential code to reduce almost half of the ROM size. With our dedicated modularization, the proposed architecture is suitable for multi-standard HDTV applications.1