Verilog-A based implementation for coupled model of single event transients in look-up table technique

Abstract

A Verilog-A based implementation of voltage coupled model is developed for Single-Event Transients (SETs) in microelectronic circuits. By implementing a look-up table in Verilog-A, the SET current source performs well and consents with the results from Technology CAD (TCAD) based mix-mode simulation. Simulation results from Synopsys Hspice 2008 indicates that the method proposed in this paper correctly reveals the current “tail” which reflects the equilibrium course of charge collection. Moreover, the Verilog-A based method speeds up the simulation by over 18,000 times than the mix-mode simulation and is also faster than the piecewise linear source (PWL). Furthermore, this Verilog-A based LUT method cooperates with the design flow well and can be easily applied to various applications with wide supports of industrial EDA tools1.