发布求助
文献互助 智能选刊 最新文献

2009 IEEE 8th International Conference on ASIC最新文献

筛选
英文 中文
Potential-induced surface stress change during the electrochemical reaction 电化学反应过程中电位诱导的表面应力变化
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351327
Jie Yang, Jia Zhou
{"title":"Potential-induced surface stress change during the electrochemical reaction","authors":"Jie Yang, Jia Zhou","doi":"10.1109/ASICON.2009.5351327","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351327","url":null,"abstract":"Electrochemically-induced changes in surface stress at the solid-liquid interface are measured using a cantilever-based sensor. We simultaneously measure the current (charge) and interfacial stress changes by employing a microcantilever as both the working electrode (in a conventional three-probe electrochemical cell configuration) and as the mechanical transducer (bending of the cantilever) when the electrochemical reaction takes place, and discuss the origin of the surface stress.1.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131680154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A super low power MICS band receiver in 65 nm CMOS for high resolution epi-retinal prosthesis 一种用于高分辨率视网膜外假体的65 nm CMOS超低功耗MICS波段接收器
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351266
Jiawei Yang, N. Tran, S. Bai, D. Ng, M. Halpern, E. Skafidas, I. Mareels
{"title":"A super low power MICS band receiver in 65 nm CMOS for high resolution epi-retinal prosthesis","authors":"Jiawei Yang, N. Tran, S. Bai, D. Ng, M. Halpern, E. Skafidas, I. Mareels","doi":"10.1109/ASICON.2009.5351266","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351266","url":null,"abstract":"We report a super low power MICS band receiver for a high resolution epi-retinal prosthesis (BionicEye). The FSK receiver consumes less than 1.5 mW power with 1 V supply. It can achieve a maximum data rate of 400 kb/s. In this paper, we present the research work carried out on designing a fully-integrated sub-threshold receiver fabricated on a 65nm CMOS chip. In order to achieve super low power consumption, more than 90% of the transistors in all analog building blocks are operated in sub-threshold region. System level issues, such as required receiver architecture and specifications are also addressed1.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"47 Suppl 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122550056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
High computing-intensive array system design and hardware implement 高计算密集型阵列系统设计与硬件实现
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351568
Y. Song, Xiaolei Wang, Wei Ni, Duoli Zhang, Gaoming Du
{"title":"High computing-intensive array system design and hardware implement","authors":"Y. Song, Xiaolei Wang, Wei Ni, Duoli Zhang, Gaoming Du","doi":"10.1109/ASICON.2009.5351568","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351568","url":null,"abstract":"This paper addresses a novel coarse grain dynamic reconfigurable computing system, called DReAC-2, design and hardware implement. A whole DReAC-2 system integrates a Nios II processor, which manages the whole reconfigurable system, and a dynamic reconfigurable coprocessor, which comprises of an 8x8 processing node array designed for high regularity, high computation-intensive tasks. Hardware prototype of DReAC-2 has been implemented on the ALTERA STRATIX II EP2S180 development board. According to task's nature, MIMD computing array can select either parallel-pipelined pattern or array-parallel pattern to gain the better performance. The experiment results show that DReAC-2 achieves much higher 10∼100x factor than NIOS II processors, and 2x∼4x factors and higher precision than some others reconfigurable processors1.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115303504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 14-bit successive-approximation AD converter with digital calibration algorithm 一种带数字校准算法的14位连续逼近模数转换器
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351481
He Yong, Wu Wuchen, Meng Hao, Zhou Zhonghua
{"title":"A 14-bit successive-approximation AD converter with digital calibration algorithm","authors":"He Yong, Wu Wuchen, Meng Hao, Zhou Zhonghua","doi":"10.1109/ASICON.2009.5351481","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351481","url":null,"abstract":"This paper implements a 14-bit successive approximation analog-to-digital converter (SAR ADC) design. The architecture and performance of the designed ADC is described. A digital calibration algorithm applied in this ADC has been emphasized in this paper. The correction codes of the calibrated capacitor are generated from the low bit to the high bit in the correction code generation state and are loaded in the calibration state. The digital control logic switches the capacitor array with the related correction code. The testing result indicates that the SAR ADC achieves a resolution of 14-bit at 200KSPS sampling rate1.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"107 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120983203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A fast-lock digital delay-locked loop controller 一种快速锁定数字延迟锁定环路控制器
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351573
Bo Ye, Tianwang Li, Xingcheng Han, Min Luo
{"title":"A fast-lock digital delay-locked loop controller","authors":"Bo Ye, Tianwang Li, Xingcheng Han, Min Luo","doi":"10.1109/ASICON.2009.5351573","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351573","url":null,"abstract":"A fast-lock digital delay-locked loop(DLL) is presented in this paper. A delay compensation circuit (DCC ) is used to achieve short lock time. The DLL's initial value is controlled by the DCC, so that initial delay time of the delay line can be located in the expected scope and there is only one stable state in various process, voltage, and temperature (PVT) conditions. Since the delay time of each delay cell changes based on the variations of PVT conditions, the output values generated by the DCC are determinate of the PVT conditions in the chip. Thus the DLL's initial state changes according to the detected PVT conditions, and the initial large phase difference is eliminated by the DCC. So it can be fast locked and only has one stable state. The proposed digital DLL overcomes the drawbacks of traditional DLL which may have more than one stable state. The HSPICE simulation results show that the proposed digital DLL circuit achieves fine accuracy and the maximum lock time is 16 clock cycles1.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121680389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Design and experimental research on shallow water volume reverberation signal acquisition system 浅水体积混响信号采集系统的设计与实验研究
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351539
Yongwei Liu, Qi Li, Mengying Chen
{"title":"Design and experimental research on shallow water volume reverberation signal acquisition system","authors":"Yongwei Liu, Qi Li, Mengying Chen","doi":"10.1109/ASICON.2009.5351539","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351539","url":null,"abstract":"Volume reverberation is the main interference of active sonar in shallow coastal waters. This greatly limits the sonar's working range and the performance of parameter estimation. A lot of research on the properties of deep scattering layer, sea surface reverberation, sea bottom reverberation has been done. However, the research on volume reverberation at 10 to 40 kHz in shallow coastal waters is only a little. It is difficult to collect shallow water volume reverberation signal by conventional underwater acoustic signal acquisition equipments with an electrical switch, due to circuit obstruction. Therefore, based on the characteristic of volume reverberation, a signal acquisition system was designed. The control core was made up of Field Programmable Gate Array (FPGA). The signal acquisition system was tested in shallow coastal waters. The law of volume backscattering intensity with temperature, salinity, the concentration of suspended sediment particles, and frequency is summarized. The results demonstrate that the volume backscattering intensity may be changed by 30 dB, due to the concentration change of suspended sediment particles.1","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"185 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124924376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Transistor permutation for better transistor chaining 晶体管排列更好的晶体管链
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351226
Xun Chen, Jianwen Zhu
{"title":"Transistor permutation for better transistor chaining","authors":"Xun Chen, Jianwen Zhu","doi":"10.1109/ASICON.2009.5351226","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351226","url":null,"abstract":"Custom layout design style remains to be an effective way of improving and differentiating the performance of integrated circuits. In this paper, we revisit the classic problem of transistor chaining, a key step in transistor level layout generation and report a systematic method for permutating transistors in a circuit topology such that without altering its logic function, the chance of finding transistor chains with minimum number of diffusion breaks is increased. The results on nontrivial circuits show that our algorithm can consistently outperform the best reported results in the literature1.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121581742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
The chip Verification method based on memory monitoring 基于内存监控的芯片验证方法
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351303
Sheng Liu, H. Yang, Yong Li, Shuming Chen
{"title":"The chip Verification method based on memory monitoring","authors":"Sheng Liu, H. Yang, Yong Li, Shuming Chen","doi":"10.1109/ASICON.2009.5351303","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351303","url":null,"abstract":"a verification method based on memory monitoring is proposed for harmonizing the execution of RTL simulator and system-level model (SLM) simulator, in the situation that the SLM is a ‘black-box’ to the designers. This method can quickly and efficiently find the differences of big benchmarks' executing process between the RTL simulation and SLM simulation, and help the verification engineers rapidly finding the bugs in the RTL codes and speedup the accomplishment of verification.1","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125190251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A zero-ESR stable adaptively biased low-dropout regulator in standard CMOS technology 标准CMOS技术中的零esr稳定自适应偏置低压差稳压器
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351178
Min Tan
{"title":"A zero-ESR stable adaptively biased low-dropout regulator in standard CMOS technology","authors":"Min Tan","doi":"10.1109/ASICON.2009.5351178","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351178","url":null,"abstract":"An adaptively biased low-dropout regulator (LDO) in standard CMOS process technology is presented. By designing the poles and zeros carefully and utilizing the adaptive biasing technique, this LDO provides high stability, good line regulation as well as fast transient response, even with zero ESR off-chip compensation capacitor1.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125668719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
An efficient verification and test scheme for media broadcasting demodulator 一种有效的媒体广播解调器验证和测试方案
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351575
Yun Chen, Nan Shao, Bo Xiang, Dan Bao, An Pan, Xiaoyang Zeng
{"title":"An efficient verification and test scheme for media broadcasting demodulator","authors":"Yun Chen, Nan Shao, Bo Xiang, Dan Bao, An Pan, Xiaoyang Zeng","doi":"10.1109/ASICON.2009.5351575","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351575","url":null,"abstract":"For the complex development process of media broadcasting demodulator chip, it is proposed that a low cost, high reliability verification and test scheme at system level in this paper. This scheme emphasizes the collaboration of algorithm simulation, RTL description, FPGA verification, ASIC realization and any other stages of chip development. All these stages constitute an organic, closely interconnected whole. And for the particularity of communication chip, this scheme can solve function verification and performance test, ensure the accuracy, completeness and reliability of the test and verification. Then both the development time and the cost of the product are significantly reduced. This verification and test scheme has been applied to the demodulation chip of the receiver of Chinese broadcasting standard DTMB system.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125678222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信