The chip Verification method based on memory monitoring

Abstract

a verification method based on memory monitoring is proposed for harmonizing the execution of RTL simulator and system-level model (SLM) simulator, in the situation that the SLM is a ‘black-box’ to the designers. This method can quickly and efficiently find the differences of big benchmarks' executing process between the RTL simulation and SLM simulation, and help the verification engineers rapidly finding the bugs in the RTL codes and speedup the accomplishment of verification.1