{"title":"标准CMOS技术中的零esr稳定自适应偏置低压差稳压器","authors":"Min Tan","doi":"10.1109/ASICON.2009.5351178","DOIUrl":null,"url":null,"abstract":"An adaptively biased low-dropout regulator (LDO) in standard CMOS process technology is presented. By designing the poles and zeros carefully and utilizing the adaptive biasing technique, this LDO provides high stability, good line regulation as well as fast transient response, even with zero ESR off-chip compensation capacitor1.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A zero-ESR stable adaptively biased low-dropout regulator in standard CMOS technology\",\"authors\":\"Min Tan\",\"doi\":\"10.1109/ASICON.2009.5351178\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An adaptively biased low-dropout regulator (LDO) in standard CMOS process technology is presented. By designing the poles and zeros carefully and utilizing the adaptive biasing technique, this LDO provides high stability, good line regulation as well as fast transient response, even with zero ESR off-chip compensation capacitor1.\",\"PeriodicalId\":446584,\"journal\":{\"name\":\"2009 IEEE 8th International Conference on ASIC\",\"volume\":\"9 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-12-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 IEEE 8th International Conference on ASIC\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASICON.2009.5351178\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 IEEE 8th International Conference on ASIC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASICON.2009.5351178","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A zero-ESR stable adaptively biased low-dropout regulator in standard CMOS technology
An adaptively biased low-dropout regulator (LDO) in standard CMOS process technology is presented. By designing the poles and zeros carefully and utilizing the adaptive biasing technique, this LDO provides high stability, good line regulation as well as fast transient response, even with zero ESR off-chip compensation capacitor1.
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