H.264视频解码的并行帧内预测结构

2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI:10.1109/ASICON.2009.5351558

Xi Wang, Xiaoxin Cui, Dunshan Yu

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引用次数: 5

摘要

本文采用了一种高效的硬件架构来实时实现H.264视频编码标准中的帧内预测算法。硬件设计是基于一种新的内部预测方程组织。与传统结构相比，提高了内部预测效率。Verilog RTL经验证可在Xilinx II FPGA1中工作在103 MHz。

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A parallel intra prediction architecture for H.264 video decoding

In this paper, an efficient hardware architecture for real-time implementation of intra prediction algorithm used in H.264 video coding standard is adopted. The hardware design is based on a novel organization of the intra prediction equations. Compared with conventional architecture, intra predict efficiency is enhanced. The Verilog RTL is verified to work at 103 MHz in a Xilinx II FPGA1.

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来源期刊

2009 IEEE 8th International Conference on ASIC

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