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2009 IEEE 8th International Conference on ASIC最新文献

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A built-in self-test high-current LED driver 内置自检大电流LED驱动器
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351429
D. H. Nguyen, J. Hasan, S. Ang
{"title":"A built-in self-test high-current LED driver","authors":"D. H. Nguyen, J. Hasan, S. Ang","doi":"10.1109/ASICON.2009.5351429","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351429","url":null,"abstract":"In this paper, a built-in self-test (BIST) high-current light-emitting-diode (LED) driver circuit is proposed. The circuit not only maintains different constant currents for multiple LED strings, but it also minimizes the conduction power dissipation by keeping the power MOSFETs in the constant-current controllers operating in the linear region. The proposed driver first acquires the current-voltage (I–V) data of the constant-current power MOSFETs and stores them into memories. These stored I–V data, along with a duty cycle control of the switching converter, are used to ensure that these power MOSFETs are operating in their linear region to minimize conduction power dissipation. The proposed circuit was verified using PSPICE with two to five LED strings. Simulation results show a maximum efficiency of 95.6%.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123470426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A unified test and debug platform for SOC design 为SOC设计提供统一的测试和调试平台
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351351
Kuen-Jong Lee, C. Chang, A. Su, Si-Yuan Liang
{"title":"A unified test and debug platform for SOC design","authors":"Kuen-Jong Lee, C. Chang, A. Su, Si-Yuan Liang","doi":"10.1109/ASICON.2009.5351351","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351351","url":null,"abstract":"As the complexity of System-on-a-Chip (SOC) design keeps growing rapidly, efficient and economic testing and debugging for complex circuits at silicon stage has become extremely important. In this paper we present a unified platform that facilitates efficient on-chip testing and silicon debugging in a PC-based environment. Test techniques including scan and BIST, and debug functions including online tracing, hardware breakpoint insertion and cycle-based single-stepping, are supported in this platform. An automatic design tool is also developed to simplify the generation and application of the platform. With this platform users can easily carry out structural testing with the scan or BIST test mode, functional verification with the on-line tracing mode, and fault diagnosis with the single-step mode.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114315646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A reconfigurable architecture for DWT and IDWT in JPEG2000 JPEG2000中DWT和IDWT的可重构结构
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351574
Hong qi, Wang Kan-wen, Cao Wei, T. Jiarong
{"title":"A reconfigurable architecture for DWT and IDWT in JPEG2000","authors":"Hong qi, Wang Kan-wen, Cao Wei, T. Jiarong","doi":"10.1109/ASICON.2009.5351574","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351574","url":null,"abstract":"In JPEG2000, 9/7 and 5/3 filters are adopted to realize DWT algorithm. In this paper, we proposed a folded reconfigurable architecture which can be used to 9/7 or 5/3 filter. It is simple and can reduce hardware usage. Further, it is efficient to be used in 2D DWT1.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"191 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116308947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design and FPGA implementation of JAVA CARD coprocessor for EMV compatible IC bankcard 兼容EMV集成电路银行卡的JAVA CARD协处理器设计与FPGA实现
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351533
Di Wu, Liji Wu, Xiangmin Zhang
{"title":"Design and FPGA implementation of JAVA CARD coprocessor for EMV compatible IC bankcard","authors":"Di Wu, Liji Wu, Xiangmin Zhang","doi":"10.1109/ASICON.2009.5351533","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351533","url":null,"abstract":"To meet the urgent need of transferring magnetic stripe bankcard to IC bankcard, a 16-bit low power JAVA CARD coprocessor for EMV compatible IC bankcard is designed and implemented by FPGA. In order to speed up the running of the JAVA CARD applets, a novel 5-stage pipelined JAVA CARD coprocessor is achieved with pure logic circuits, which carries out the execution of 88 instructions out of 134 defined in the JAVA CARD Virtual Machine Specification 3.0 Classic Edition, while the remaining instructions are processed by the main 32-bit RISC processor. A pre-fetch instruction buffer and stack-top-register are used to ensure the fluency of the pipeline for accelerating the coprocessor. The design is verified to be feasible for the need of IC bankcard by FPGA and proved significantly faster than the regular software virtual machine, while remaining in a low power consumption level1.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114746174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Semi-distributed scheduling for flexible codeword assignment in a CDMA Network-on-Chip CDMA片上网络中灵活码字分配的半分布式调度
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351263
Woojoong Lee, G. Sobelman
{"title":"Semi-distributed scheduling for flexible codeword assignment in a CDMA Network-on-Chip","authors":"Woojoong Lee, G. Sobelman","doi":"10.1109/ASICON.2009.5351263","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351263","url":null,"abstract":"Flexible codeword assignment in a Code Division Multiple Access (CDMA) switch allows advanced capabilities to be included within a Network-on-Chip (NoC). However, frequent codeword assignment with small size packets can reduce the performance of the network. In this paper, we propose a novel semi-distributed scheduling technique to improve the performance by reducing the need to access the codeword pool. The proposed switch design has been synthesized using a 0.13 micron technology library. Comparative synthesis and simulation results are provided.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114775963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Full coverage location of logic resource faults in A SOC co-verification technology based FPGA functional test environment 基于SOC协同验证技术的FPGA功能测试环境中逻辑资源故障的全覆盖定位
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351202
Y. Liao, P. Li, A. Ruan, W. Li, W.C. Li
{"title":"Full coverage location of logic resource faults in A SOC co-verification technology based FPGA functional test environment","authors":"Y. Liao, P. Li, A. Ruan, W. Li, W.C. Li","doi":"10.1109/ASICON.2009.5351202","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351202","url":null,"abstract":"Full coverage location of logic resource faults is vital for FPGA design and fabrication, rather than only detecting whether there are faults or not. Taking advantage of flexibility and observability of software in conjunction with high-speed simulation of hardware, SOC co-verification technology based in-house FPGA functional test environment embedded with an in-house computerized tool, ConPlacement, can locate logic resources automatically, exhaustively and repeatedly. The approach to implement full coverage location of configurable logic block (CLB) faults by the FPGA functional test environment is presented in the paper. Experimental results of XC4010E demonstrate that full coverage location of logic resource faults as well as multi-faults position can be realized.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127663422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Coupling noise analysis technique using random walks 随机游走耦合噪声分析技术
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351315
H. Miwa, G. Suzuki
{"title":"Coupling noise analysis technique using random walks","authors":"H. Miwa, G. Suzuki","doi":"10.1109/ASICON.2009.5351315","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351315","url":null,"abstract":"Random walk method has recently been proposed in signal integrity analysis such as power grid noise analysis. This paper proposes techniques to apply random walk method to signal noise analysis for the data path circuit containing non-linear buffers and coupling capacitors. In order to fix output voltages and currents of non-linear buffer outputs, relaxation process is employed. To analyze coupling noise of both aggressors and victims, relaxation process is also introduced. The walk reward sharing technique improves computational efficiency by 6.2 times. In coupling noise analysis of example circuit, average voltage error of the coupling noise was 1.34% in 60 analysis timesteps and 50% delay error was 0.66% compared to SPICE. To analyze one timestep, average CPU time is 67 (ms) and the number of walks is 20,100 in 60 analysis timesteps.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"89 11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128004357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A mixed-signal calibration technology for the pipeline A/D converter 管道A/D转换器的混合信号校准技术
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351477
Shangquan Liang, Yongsheng Yin, Honghui Deng, Xiao-lei Wang, Minglun Gao
{"title":"A mixed-signal calibration technology for the pipeline A/D converter","authors":"Shangquan Liang, Yongsheng Yin, Honghui Deng, Xiao-lei Wang, Minglun Gao","doi":"10.1109/ASICON.2009.5351477","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351477","url":null,"abstract":"A mixed-signal calibration architecture and algorithm based upon 14bits 1.5b/s pipeline A/D converter is proposed1. The mixed-signal calibration algorithm consists of analog domain calibration and digital domain calibration. The analog-domain calibration algorithm adopts the level shifting technology to shift the input signal to lower voltage range. The digital output is reconstructed in the digital-domain after analog-to-digital conversion. The digital-domain calibration algorithm adopts code-by-code compensation technique and constructs a linear equation by the method of awaiting determined coefficients. An error calibration look-up table is acquired through the digital-domain calibration. A behavioral-level model of 14bits 1.5b/s pipeline ADC with mixed-signal calibration algorithm is established. The results show that the proposed calibration architecture and algorithm can effectively calibrate errors. The INL and DNL are reduced within ±0.5LSB. The SNDR is improved from 30.8dB to 84.5dB, and the ENOB is arrived to 13.74bits.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125971197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 2.45GHz CMOS power amplifier with high linearity 一种2.45GHz高线性CMOS功率放大器
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351413
Mingfu Zhao, Lingling Sun, J. Wen, Zhiping Yu, Jin Kang
{"title":"A 2.45GHz CMOS power amplifier with high linearity","authors":"Mingfu Zhao, Lingling Sun, J. Wen, Zhiping Yu, Jin Kang","doi":"10.1109/ASICON.2009.5351413","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351413","url":null,"abstract":"A 2.45GHz 0.18µm RF CMOS Class-AB power amplifier (PA) with high linearity and output power for WLAN is presented in this paper. The proposed power amplifier is implemented with a two-stage architecture which is followed by an off-chip output matching network. To improve the linearity, an integrated diode linearization circuit provides a compensation mechanism for the input capacitance variation of the active devices, improving the linearity from the gain compressing. Moreover, a simple LC second harmonic tank and optimum gate biasing point is applied for the cancellation of the nonlinear harmonic generated by gm. In order to demonstrate the feasibility of the technique, two types of PAs have been designed. The improved PA at 2.4V supply voltage, has a 22.5dB of power gain,5 dBm increase of P1dB, 15% and 5dB improvement of PAE at P1dB and IMD3, respectively, as compared with the traditional PA‥","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127879336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
An energy-aware heuristic constructive mapping algorithm for Network on Chip 片上网络的能量感知启发式构造映射算法
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351596
Yancang Chen, Lunguo Xie, Jinwen Li
{"title":"An energy-aware heuristic constructive mapping algorithm for Network on Chip","authors":"Yancang Chen, Lunguo Xie, Jinwen Li","doi":"10.1109/ASICON.2009.5351596","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351596","url":null,"abstract":"Network on Chip (NoC) is a promising interconnection solution for the ever-increasing systems complexity and design productivity gap. Mapping the IP cores onto a given platform is an important phase of NoC design which can greatly affect the performance and energy consumption of the chip. In this paper, we analyze the preexistent mapping algorithms, and categorize them into three classes according to the tracks of obtaining the near-optimal mapping. We present a fast hybrid heuristic constructive algorithm, i.e. CMAP, to map cores onto NoC architectures with the goal of minimizing the total communication energy consumption. The algorithm is applied to two real applications and a series of task graphs generated by TGFF package. The accuracy, efficiency and scalability of the proposed algorithm are confirmed by comparing the results of our algorithm with other mapping algorithms1.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127912113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
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