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2009 IEEE 8th International Conference on ASIC最新文献

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An UHF RFID transponder for ISO 18000-6B 符合ISO 18000-6B标准的超高频RFID转发器
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351528
Xiaoxing Feng, Xin'an Wang, Xing Zhang, Binjie Ge, Jinpeng Shen, Shan Liu, Yongzhen Qi, Jinsi Zhong
{"title":"An UHF RFID transponder for ISO 18000-6B","authors":"Xiaoxing Feng, Xin'an Wang, Xing Zhang, Binjie Ge, Jinpeng Shen, Shan Liu, Yongzhen Qi, Jinsi Zhong","doi":"10.1109/ASICON.2009.5351528","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351528","url":null,"abstract":"An UHF Radio Frequency Identification (RFID) transponder complying with Chinese UHF RFID band setting is presented in this paper. The RFID transponder is composed of analog-RF front-end and digital signal processing unit. The analog-RF front-end is mainly made up of voltage multiplier, limiter, power-on-reset (POR), clock generator, demodulator and modulator. This work proposes a novel clock generating scheme with features of area effective and high precision which uses ring oscillator and counter, accompanying preamble sent by reader before data communication. Clock generator drives transponder with clock variation less than ± 1.76% which is below ±15% requested by standard. Besides, a new demodulator is presented in this paper. Silicon area of demodulator is only 21% of traditional structure and it could demodulate input signal with data rate ranging from 10Kbps to 870Kbps. Full chip area without test pads is 0.7mm2@0.18um CMOS process and consumes 15uW without Memory.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121758914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
High speed and low power ADC design with dynamic analog circuits 采用动态模拟电路的高速低功耗ADC设计
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351489
A. Matsuzawa
{"title":"High speed and low power ADC design with dynamic analog circuits","authors":"A. Matsuzawa","doi":"10.1109/ASICON.2009.5351489","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351489","url":null,"abstract":"This paper discusses high speed and low power ADC design with dynamic analog circuits. An OpAmp based ADC design is no longer useful in nano-meter CMOS era and a comparator based ADC design becomes dominant for ADC design along with technology scaling. Offset mismatch and input referred noise in a comparator affects ENOB seriously. Furthermore conversion speed, energy consumption and occupied area have a serious tradeoff in ENOB. A digital offset mismatch compensation technique accommodates this trade off, however accuracy is not sufficient and more effective technique should be developed. An equation to estimate the input referred noise in dynamic comparator has been deduced and it suggests that the noise can be reduce by increase of load capacitance and reduction of the effective gate voltage. However higher resolution than 10 bit looks not easy. Technology development is required to realize higher resolution ADC1.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132423089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Clocked storage elements robust to process variations 时钟存储元件对过程变化的鲁棒性
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351566
Joosik Moon, M. Aktan, V. Oklobdzija
{"title":"Clocked storage elements robust to process variations","authors":"Joosik Moon, M. Aktan, V. Oklobdzija","doi":"10.1109/ASICON.2009.5351566","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351566","url":null,"abstract":"In this work, different types of clocked storage elements are compared in terms of the impact of process variations on their performances. Transistor sizes are obtained from energy-efficient characteristics and used in the simulation to measure the delay variations caused by process variations. The structure of a clocked storage element affects its robustness to process variations.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133832042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
High linearity voltage-controlled oscillator 高线性压控振荡器
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351417
Nguyen Phuong Thi Le, Ken Tatt Low, L. Yao
{"title":"High linearity voltage-controlled oscillator","authors":"Nguyen Phuong Thi Le, Ken Tatt Low, L. Yao","doi":"10.1109/ASICON.2009.5351417","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351417","url":null,"abstract":"A linearization technique for CMOS voltage-controlled oscillators (VCOs) is presented. The linearity of the oscillator is improved by applying a feedback loop using a switched-capacitor network as a frequency-to-voltage converter (FVC). The technique is verified by circuit-level simulation using parameters of a 0.35-µm CMOS technology. After the linearization, the linearity error of VCO can be improved to less than 0.015% for a dynamic range of 60 dB.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133889259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A simple parameter extraction method for on-chip inductors 一种简单的片上电感参数提取方法
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351381
Xiaoming Lu, Jingtian Xi, N. Yan, Hao Min
{"title":"A simple parameter extraction method for on-chip inductors","authors":"Xiaoming Lu, Jingtian Xi, N. Yan, Hao Min","doi":"10.1109/ASICON.2009.5351381","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351381","url":null,"abstract":"In this paper a simple parameter extraction method is proposed. The extraction method is applied to extract parameters from the measured or simulated S-parameters of on-chip inductors fabricated with SMIC 0.18um CMOS RF technology. The result shows a good agreement with the measured or simulated data over a wide frequency range without any optimization.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133991045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 15-µs fast-locking frequency synthesizer for reconfigurable wireless systems 用于可重构无线系统的15µs快速锁定频率合成器
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351422
Junhua Liu, H. Liao, Ru Huang
{"title":"A 15-µs fast-locking frequency synthesizer for reconfigurable wireless systems","authors":"Junhua Liu, H. Liao, Ru Huang","doi":"10.1109/ASICON.2009.5351422","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351422","url":null,"abstract":"A fast-locking wideband CMOS frequency synthesizer for reconfigurable wireless applications is presented. An analog coarse tuning loop with a large loop bandwidth is used for fast locking, and new adaptive loop filters are proposed to stabilize the coarse tuning voltage when the loop is switched off. The frequency synthesizer with a 1.95–2.6 GHz frequency range is fabricated in 0.18µm CMOS process and achieves a settling time of 15-µs with loop bandwidth of 100 kHz. So far as we know, this is the fastest locking speed for wideband frequency synthesizers with the same loop bandwidth.1","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"132 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134171512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Effectiveness analysis of low power technique of dynamic logic under temperature and process Variations 温度和工艺变化下动态逻辑低功耗技术的有效性分析
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351206
Jinhui Wang, Wu-chen Wu, Na Gong, Wang Zhang, L. Hou
{"title":"Effectiveness analysis of low power technique of dynamic logic under temperature and process Variations","authors":"Jinhui Wang, Wu-chen Wu, Na Gong, Wang Zhang, L. Hou","doi":"10.1109/ASICON.2009.5351206","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351206","url":null,"abstract":"Using multiple-parameter Monte Carlo method, the effectiveness of the dual threshold voltage technique (DTV) in low power domino logic design is analyzed. Simulation results indicate that under significant temperature and process variations, DTV is still highly effective to reduce the total leakage and active power consumption for domino gates with speed loss. Also, regarding power and delay characteristics, different structure domino gates with DTV have different robustness against the temperature and process variation1.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130734492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Least operation traversal method applied in optimization of logic circuits 最小运算遍历法在逻辑电路优化中的应用
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351553
Huihong Zhang, Pengjun Wang, Xingsheng Gu, Jing Dai
{"title":"Least operation traversal method applied in optimization of logic circuits","authors":"Huihong Zhang, Pengjun Wang, Xingsheng Gu, Jing Dai","doi":"10.1109/ASICON.2009.5351553","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351553","url":null,"abstract":"In order to improve the optimization of middle and large-scale logic circuits, a heuristic inspired traversal method of circuit polarities called the least operation traversal method (LOTM) is proposed. Firstly, the polarity traversal sequence problem of fixed-polarity RM circuits is analyzed and a mathematical model of the problem is given and discussed; Secondly, the detailed realization of the LOTM is explained; finally, the method embedded in genetic algorithm is tested by 10 circuits from MCNC Benchmark. The results show that the method can significantly improve the efficiency of genetic algorithm for circuit optimization, especially for circuits with a number of inputs or complex structure1.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"181 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133287370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A systolic architecture with linear space complexity for longest common subsequence problem 一种具有线性空间复杂度的最长公共子序列问题的收缩结构
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351612
Chuanpeng Chen, Zhongping Qin
{"title":"A systolic architecture with linear space complexity for longest common subsequence problem","authors":"Chuanpeng Chen, Zhongping Qin","doi":"10.1109/ASICON.2009.5351612","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351612","url":null,"abstract":"The longest common subsequence (LCS) problem is to find an LCS of two strings and the length of the LCS (LLCS). Many previous works focused on reducing the processing time. However, most require too large memory space in total, resulting in being not suitable for hardware implementation. In this paper, we propose a hardware-implementable algorithm and its systolic architecture. The algorithm achieves linear space complexity, and the systolic architecture is feasible for hardware implementation. For two given strings with their lengths of m and n, the algorithm consumes less time complexity when the LLCS is approaching to the minimum of m and n. Furthermore, a scalable architecture is proposed to deal with the LCS problems of two huge strings, whose lengths are far more than m and n. Therefore, our scalable systolic architecture with linear space complexity for the LCS problem is suitable for hardware implementation, and the synthesized results show that our architecture is more efficient.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":" 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132159636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A switched-inductor based VCO with an ultra-wideband tuning range of 87.6 % 一种基于开关电感的压控振荡器，超宽带调谐范围为87.6%
2009 IEEE 8th International Conference on ASIC Pub Date : 2009-12-11 DOI: 10.1109/ASICON.2009.5351421
Liu Qing, S. Jiangtao, S. Kurachi, N. Itoh, T. Yoshimasu
{"title":"A switched-inductor based VCO with an ultra-wideband tuning range of 87.6 %","authors":"Liu Qing, S. Jiangtao, S. Kurachi, N. Itoh, T. Yoshimasu","doi":"10.1109/ASICON.2009.5351421","DOIUrl":"https://doi.org/10.1109/ASICON.2009.5351421","url":null,"abstract":"A novel switched-inductor based resonator is proposed to implement an ultra-wideband VCO. The VCO is designed and fabricated using 0.13 µm CMOS and fully evaluated on wafer. The measured results show that the proposed VCO has a tuning range as high as 87.6% spanning from 1.81 GHz to 4.63 GHz. The measured phase noise of −124.4 dBc/Hz at 1 MHz offset from the 1.81 GHz carrier is obtained 1.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"344 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133210842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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