{"title":"A sub-1V 115nA 0.35µm CMOS voltage reference for ultra low-power applications","authors":"Haifeng Ma, F. Zhou","doi":"10.1109/ASICON.2009.5351397","DOIUrl":null,"url":null,"abstract":"A voltage reference circuit capable of sub-1V operation and with ultra-low power consumption is introduced in this paper. In the proposed circuit, proportional-to-absolute-temperature voltage is generated by using the series-connection of two NMOS devices working in sub-threshold region and the gate-to-source voltage of another NMOS device is adopted to realize the complementary-to-absolute-temperature voltage. Moreover, the temperature compensation is performed by using a switch-capacitor circuit. The proposed circuit is implemented in Chartered 0.35µm CMOS technology and occupies an active chip area of 0.021mm2. Post-layout simulation results show that it can operate with a supply voltage down to 0.9V while consuming 115nA ground current. With 1V power supply, the output voltage is 142.8mV at 25 °C and the temperature coefficient is 25.5ppm/°C1.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"33 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 IEEE 8th International Conference on ASIC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASICON.2009.5351397","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 12
Abstract
A voltage reference circuit capable of sub-1V operation and with ultra-low power consumption is introduced in this paper. In the proposed circuit, proportional-to-absolute-temperature voltage is generated by using the series-connection of two NMOS devices working in sub-threshold region and the gate-to-source voltage of another NMOS device is adopted to realize the complementary-to-absolute-temperature voltage. Moreover, the temperature compensation is performed by using a switch-capacitor circuit. The proposed circuit is implemented in Chartered 0.35µm CMOS technology and occupies an active chip area of 0.021mm2. Post-layout simulation results show that it can operate with a supply voltage down to 0.9V while consuming 115nA ground current. With 1V power supply, the output voltage is 142.8mV at 25 °C and the temperature coefficient is 25.5ppm/°C1.