The gate-bias influence for ESD characteristic of NMOS

Abstract

The positive and negative gate-bias effect on ESD robustness of NMOS devices are analyzed respectively in this paper. The influence of gate-bias have been simulated by ISE TCAD and discussed. The simulation results indicate that the triggering voltage fell from 10.46V to 7.8V with the negative gate bias changed from 0V to −10V, and reduced from 10.46V to 5.92V with the positive gate bias changed from 0V to 3V. Under appropriate gate bias, the ESD protection devices can obtain lower Vt1 and higher Vt2. It gives benefit of triggering the large-dimension MOS uniformly, which can improve ESD robustness directly.