采用间接反馈补偿运算放大器的低压高性能cmos电流反馈放大器的设计

R. Nandwana, Mahima Arrawatia, Nilesh Goel
{"title":"采用间接反馈补偿运算放大器的低压高性能cmos电流反馈放大器的设计","authors":"R. Nandwana, Mahima Arrawatia, Nilesh Goel","doi":"10.1109/ASICON.2009.5351474","DOIUrl":null,"url":null,"abstract":"In this paper low-voltage high performance CMOS Current Feedback Amplifier is designed using indirect feedback compensated operational amplifier and the results are compared with the existing topology. The Operational-Amplifier used has the open loop gain of 101.8 dB with 25ns settling time, unity gain bandwidth 169.8 MHz, phase margin 70° with rail to rail output swing. The CMOS-Current Feedback Amplifier designed using this Operational-Amplifier has nearly gain independent bandwidth with settling time observed as 44 ns and slew rate increment up to 20V/µs. The circuit is designed at 0.18µm Digital CMOS process with supply voltage 1.8 volt.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"125 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Design of low-voltage high performance CMOS-Current feedback amplifier using indirect feedback compensated Op-Amp\",\"authors\":\"R. Nandwana, Mahima Arrawatia, Nilesh Goel\",\"doi\":\"10.1109/ASICON.2009.5351474\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper low-voltage high performance CMOS Current Feedback Amplifier is designed using indirect feedback compensated operational amplifier and the results are compared with the existing topology. The Operational-Amplifier used has the open loop gain of 101.8 dB with 25ns settling time, unity gain bandwidth 169.8 MHz, phase margin 70° with rail to rail output swing. The CMOS-Current Feedback Amplifier designed using this Operational-Amplifier has nearly gain independent bandwidth with settling time observed as 44 ns and slew rate increment up to 20V/µs. The circuit is designed at 0.18µm Digital CMOS process with supply voltage 1.8 volt.\",\"PeriodicalId\":446584,\"journal\":{\"name\":\"2009 IEEE 8th International Conference on ASIC\",\"volume\":\"125 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-12-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 IEEE 8th International Conference on ASIC\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASICON.2009.5351474\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 IEEE 8th International Conference on ASIC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASICON.2009.5351474","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3

摘要

本文采用间接反馈补偿运算放大器设计了低压高性能CMOS电流反馈放大器,并与现有拓扑结构进行了比较。所使用的运算放大器开环增益为101.8 dB,稳定时间为25ns,单位增益带宽为169.8 MHz,相位裕度为70°,轨到轨输出摆幅。采用该运算放大器设计的cmos电流反馈放大器具有几乎增益无关的带宽,稳定时间为44 ns,摆压速率增量可达20V/µs。电路采用0.18µm数字CMOS工艺设计,电源电压为1.8伏。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Design of low-voltage high performance CMOS-Current feedback amplifier using indirect feedback compensated Op-Amp
In this paper low-voltage high performance CMOS Current Feedback Amplifier is designed using indirect feedback compensated operational amplifier and the results are compared with the existing topology. The Operational-Amplifier used has the open loop gain of 101.8 dB with 25ns settling time, unity gain bandwidth 169.8 MHz, phase margin 70° with rail to rail output swing. The CMOS-Current Feedback Amplifier designed using this Operational-Amplifier has nearly gain independent bandwidth with settling time observed as 44 ns and slew rate increment up to 20V/µs. The circuit is designed at 0.18µm Digital CMOS process with supply voltage 1.8 volt.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信