{"title":"一种具有频率调谐字预置和校准的新型快速稳定ADPLL结构","authors":"Weicheng Zhang, Xuan Dai, J. Jin, Jianjun J. Zhou","doi":"10.1109/ASICON.2009.5351165","DOIUrl":null,"url":null,"abstract":"A time domain behavior modeling for fast-settling all digital phase-locked-loop (ADPLL) is proposed. By using the frequency presetting and adaptive bandwidth algorithm, this ADPLL can lock within 2µs according to the Simulink behavior simulation results. A digital frequency presetting module with self-calibration is presented for the frequency presetting method. An improved digital phase/frequency detector and locking detector are also included for the enhancement of fast settling1.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"102 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A novel fast-settling ADPLL architecture with frequency tuning word presetting and calibration\",\"authors\":\"Weicheng Zhang, Xuan Dai, J. Jin, Jianjun J. Zhou\",\"doi\":\"10.1109/ASICON.2009.5351165\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A time domain behavior modeling for fast-settling all digital phase-locked-loop (ADPLL) is proposed. By using the frequency presetting and adaptive bandwidth algorithm, this ADPLL can lock within 2µs according to the Simulink behavior simulation results. A digital frequency presetting module with self-calibration is presented for the frequency presetting method. An improved digital phase/frequency detector and locking detector are also included for the enhancement of fast settling1.\",\"PeriodicalId\":446584,\"journal\":{\"name\":\"2009 IEEE 8th International Conference on ASIC\",\"volume\":\"102 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-12-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 IEEE 8th International Conference on ASIC\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASICON.2009.5351165\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 IEEE 8th International Conference on ASIC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASICON.2009.5351165","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A novel fast-settling ADPLL architecture with frequency tuning word presetting and calibration
A time domain behavior modeling for fast-settling all digital phase-locked-loop (ADPLL) is proposed. By using the frequency presetting and adaptive bandwidth algorithm, this ADPLL can lock within 2µs according to the Simulink behavior simulation results. A digital frequency presetting module with self-calibration is presented for the frequency presetting method. An improved digital phase/frequency detector and locking detector are also included for the enhancement of fast settling1.
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