{"title":"Design of low-voltage high performance CMOS-Current feedback amplifier using indirect feedback compensated Op-Amp","authors":"R. Nandwana, Mahima Arrawatia, Nilesh Goel","doi":"10.1109/ASICON.2009.5351474","DOIUrl":null,"url":null,"abstract":"In this paper low-voltage high performance CMOS Current Feedback Amplifier is designed using indirect feedback compensated operational amplifier and the results are compared with the existing topology. The Operational-Amplifier used has the open loop gain of 101.8 dB with 25ns settling time, unity gain bandwidth 169.8 MHz, phase margin 70° with rail to rail output swing. The CMOS-Current Feedback Amplifier designed using this Operational-Amplifier has nearly gain independent bandwidth with settling time observed as 44 ns and slew rate increment up to 20V/µs. The circuit is designed at 0.18µm Digital CMOS process with supply voltage 1.8 volt.","PeriodicalId":446584,"journal":{"name":"2009 IEEE 8th International Conference on ASIC","volume":"125 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 IEEE 8th International Conference on ASIC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASICON.2009.5351474","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
In this paper low-voltage high performance CMOS Current Feedback Amplifier is designed using indirect feedback compensated operational amplifier and the results are compared with the existing topology. The Operational-Amplifier used has the open loop gain of 101.8 dB with 25ns settling time, unity gain bandwidth 169.8 MHz, phase margin 70° with rail to rail output swing. The CMOS-Current Feedback Amplifier designed using this Operational-Amplifier has nearly gain independent bandwidth with settling time observed as 44 ns and slew rate increment up to 20V/µs. The circuit is designed at 0.18µm Digital CMOS process with supply voltage 1.8 volt.