1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)最新文献_第3页

A smart CMOS imager with pixel level PWM signal processing 具有像素级PWM信号处理的智能CMOS成像仪

1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326) Pub Date : 1999-06-17 DOI: 10.1109/VLSIC.1999.797265

M. Nagata, M. Homma, Noriaki Takeda, Takashi Morie, Atsushi Iwata

引用次数: 19

Gain cell block architecture for gigabit-scale chain ferroelectric RAM 千兆级链铁电RAM的增益单元块结构

1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326) Pub Date : 1999-06-17 DOI: 10.1109/VLSIC.1999.797251

D. Takashima, Y. Oowaki, I. Kunishima

{"title":"Gain cell block architecture for gigabit-scale chain ferroelectric RAM","authors":"D. Takashima, Y. Oowaki, I. Kunishima","doi":"10.1109/VLSIC.1999.797251","DOIUrl":"https://doi.org/10.1109/VLSIC.1999.797251","url":null,"abstract":"Summary form only given. A ferroelectric RAM (FRAM), especially a chain FRAM, has great potential for future high-density nonvolatile memory. However, two severe problems inherent to ferroelectric material make it difficult to realize gigabit scale FRAMs; cell polarization decreases drastically in scaled FRAMs, 1) because the cell polarization does not increase by thinning the ferroelectric film, and 2) because the three-dimensional ferroelectric capacitor is difficult to make. Therefore, a sufficient cell signal will not be obtained in 256 Mb FRAMs and beyond. The gain cell approach shown can be a solution for this problem because a large cell signal is obtained even with small cell polarization due to small load capacitance. However, a memory cell using a ferroelectric FET has drawbacks such as fabrication difficulty, poor data retention and read/write disturb. A memory cell composed of a gain transistor, a write transistor, a ferroelectric capacitor and a load capacitor, realizes stable read/write operation. However the memory cell size is very large. The concept of a new gain cell block is proposed. The gain cell block contains two chain cell blocks and a gain unit composed of a gain transistor and a write transistor. The gain unit is shared by the two chain cell blocks. This configuration realizes both a large readout cell signal and a small average cell size.","PeriodicalId":433264,"journal":{"name":"1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127666065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

10-100 Gb/s throughput CMOS techniques 10-100 Gb/s吞吐量CMOS技术

1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326) Pub Date : 1999-06-17 DOI: 10.1109/VLSIC.1999.797238

C. Svensson, A. Edman

引用次数: 1

A 12.4 mW CMOS front-end for a 5 GHz wireless-LAN receiver 12.4 mW CMOS前端，用于5ghz无线局域网接收器

1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326) Pub Date : 1999-06-17 DOI: 10.1109/VLSIC.1999.797245

H. Samavati, H. Rategh, T. Lee

引用次数: 18

A high-voltage output buffer fabricated on a 2 V CMOS technology 一种基于2v CMOS技术的高压输出缓冲器

1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326) Pub Date : 1999-06-17 DOI: 10.1109/VLSIC.1999.797236

L. Clark

引用次数: 15

A low-power multi-gigabit CMOS/SIMOX LSI design using two power supply voltages 采用双电源电压的低功耗多千兆CMOS/SIMOX LSI设计

1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326) Pub Date : 1999-06-17 DOI: 10.1109/VLSIC.1999.797223

Y. Ohtomo, H. Sawada, T. Ohno, Y. Sakakibara, Y. Sato, T. Ishihara, S. Matsuoka, M. Shimaya

引用次数: 5

A wideband bandpass sigma-delta modulator for wireless applications 用于无线应用的宽带带通σ - δ调制器

1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326) Pub Date : 1999-06-17 DOI: 10.1109/VLSIC.1999.797246

A. Tabatabaei, B. Wooley

引用次数: 25

A multiple vendor 2.5-V DLL for 1.6-GB/s RDRAMs 多厂商2.5 v DLL，支持1.6 gb /s rdram

1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326) Pub Date : 1999-06-17 DOI: 10.1109/VLSIC.1999.797268

C. Portmann, A. Chu, N. Hays, S. Sidiropoulos, D. Stark, P. Chau, K. Donnelly, B. Garlepp

引用次数: 9

A 5 GHz, 32 mW CMOS frequency synthesizer with an injection locked frequency divider 5 GHz, 32毫瓦CMOS频率合成器与注入锁定分频器

1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326) Pub Date : 1999-06-17 DOI: 10.1109/VLSIC.1999.797255

H. Rategh, H. Samavati, Thomas H. Lee

引用次数: 15

A Precharged-Capacitor-Assisted Sensing (PCAS) scheme with novel level controller for low power DRAMs 一种具有新型液位控制器的低功耗dram预充电容辅助传感(PCAS)方案

1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326) Pub Date : 1999-06-17 DOI: 10.1109/VLSIC.1999.797258

T. Kono, T. Hamamoto, K. Mitsui, Y. Konishi

{"title":"A Precharged-Capacitor-Assisted Sensing (PCAS) scheme with novel level controller for low power DRAMs","authors":"T. Kono, T. Hamamoto, K. Mitsui, Y. Konishi","doi":"10.1109/VLSIC.1999.797258","DOIUrl":"https://doi.org/10.1109/VLSIC.1999.797258","url":null,"abstract":"Summary form only given. Low power consumption of DRAMs is of great concern as handheld communication tools are widely used in various environments. The combination of Voltage-Down-Convertor (VDC) and Boosted Sense Ground (BSG) scheme meets the demand because it has advantages of: 1) reduction of voltage swing of bit-lines (BLs); 2) suppression of junction leakage current of memory cells because of needlessness of substrate bias; 3) decrease of subthreshold leakage current of memory cells because of negative gate-source voltage (Vgs) of an access transistor. It can lower the active current, extend the data retention time, and reduce the data retention current. The scheme, however, has some drawbacks. First, the smaller the voltage swing on BLs is, the slower the sense speed is. Second, BSG level (Vbsg) should be stable and tolerant of GND noise because the level difference between Vbsg and GND is small. This paper proposes a new scheme to solve these problems, called a Precharged-Capacitor-Assisted Sensing (PCAS) scheme. By adopting this scheme, proper voltage level on BLs can be generated stably with faster sense speed without losing the advantages of the conventional scheme.","PeriodicalId":433264,"journal":{"name":"1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116643295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2