1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)最新文献

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Wide tuning range inversion-mode gated varactor and its application on a 2-GHz VCO 宽调谐范围逆模门控变容管及其在2ghz压控振荡器上的应用
1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326) Pub Date : 1999-06-17 DOI: 10.1109/VLSIC.1999.797233
W. Wong, F. Hui, Zhiheng Chen, J. Lau
{"title":"Wide tuning range inversion-mode gated varactor and its application on a 2-GHz VCO","authors":"W. Wong, F. Hui, Zhiheng Chen, J. Lau","doi":"10.1109/VLSIC.1999.797233","DOIUrl":"https://doi.org/10.1109/VLSIC.1999.797233","url":null,"abstract":"This paper presents a novel inversion-mode three-terminal varactor with a capacitance ranging from 0.7 pF to 2.3 pF, achieving a /spl plusmn/53% variation in the capacitance. The new device is implemented in a 0.35-/spl mu/m standard CMOS process. The measured quality factor is 22 at 2 GHz. A 2-GHz VCO is designed with this new varactor and is able to achieve a tuning range of 320 MHz with a maximum tuning gain of 220 MHz/V.","PeriodicalId":433264,"journal":{"name":"1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124836527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Charge sharing concept for power efficiency and EME improvement of boosted charge pumps in NVMs NVMs中升压电荷泵的功率效率和EME改进的电荷共享概念
1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326) Pub Date : 1999-06-17 DOI: 10.1109/VLSIC.1999.797225
C. Lauterbach, W. Weber, D. Rømer, M. Huber
{"title":"Charge sharing concept for power efficiency and EME improvement of boosted charge pumps in NVMs","authors":"C. Lauterbach, W. Weber, D. Rømer, M. Huber","doi":"10.1109/VLSIC.1999.797225","DOIUrl":"https://doi.org/10.1109/VLSIC.1999.797225","url":null,"abstract":"A new power saving concept for boosted charge pumps is introduced, which combines two-step charging, charge sharing and a simplified clocking scheme to double the power efficiency. Simultaneously, the peak value of the charging current is reduced by a factor of 3, improving the EME behaviour significantly.","PeriodicalId":433264,"journal":{"name":"1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)","volume":"1076 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122893847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 50 Gb/s 32/spl times/32 CMOS crossbar chip using asymmetric serial links 采用非对称串行链路的50gb /s 32/spl倍/32 CMOS交叉条芯片
1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326) Pub Date : 1999-06-17 DOI: 10.1109/VLSIC.1999.797221
Kun-Yung Ken Chang, Shang-Tse Chuang, N. McKeown, M. Horowitz
{"title":"A 50 Gb/s 32/spl times/32 CMOS crossbar chip using asymmetric serial links","authors":"Kun-Yung Ken Chang, Shang-Tse Chuang, N. McKeown, M. Horowitz","doi":"10.1109/VLSIC.1999.797221","DOIUrl":"https://doi.org/10.1109/VLSIC.1999.797221","url":null,"abstract":"A 32/spl times/32 synchronous crossbar chip was designed in a 0.27 /spl mu/m CMOS technology for use in a high-speed network switch. The crossbar chip uses 32 Asymmetric Serial Links to achieve high speed at the interfaces and to reduce both power and area. The crossbar switch core is implemented with static CMOS multi-stage multiplexers with multicast capability. The chip operates successfully with links running at 1.6 Gb/s. The measured bit-error-rate is <10/sup -14/ when all channels and the switch core are operating. The crossbar chip consumes 5 W and provides a total bandwidth above 50 Gb/s.","PeriodicalId":433264,"journal":{"name":"1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)","volume":"175 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114431051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A DRAM system for consistently reducing CPU wait cycles 一种持续减少CPU等待周期的DRAM系统
1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326) Pub Date : 1999-06-17 DOI: 10.1109/VLSIC.1999.797261
Y. Kanno, H. Mizuno, T. Watanabe
{"title":"A DRAM system for consistently reducing CPU wait cycles","authors":"Y. Kanno, H. Mizuno, T. Watanabe","doi":"10.1109/VLSIC.1999.797261","DOIUrl":"https://doi.org/10.1109/VLSIC.1999.797261","url":null,"abstract":"This paper describes a DRAM system for consistently reducing CPU wait cycles for an access to DRAMs in a cache-based memory hierarchy. An arithmetical address mapping circuitry and a pseudo dual-port DRAM access protocol provide a DRAM access without a bank conflict and high speed write-back accesses (write for dirty data and read for cache-line filling). Only two adders for the address mapping circuitry and a data-preload register in each DRAM are necessary for the implementation.","PeriodicalId":433264,"journal":{"name":"1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130500432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A robust 8F/sup 2/ ferroelectric RAM cell with depletion device (DeFeRAM) 带耗尽器件的8F/sup /铁电RAM电池
1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326) Pub Date : 1999-06-17 DOI: 10.1109/VLSIC.1999.797250
G. Braun, H. Hoenigschmid, T. Schlager, W. Weber
{"title":"A robust 8F/sup 2/ ferroelectric RAM cell with depletion device (DeFeRAM)","authors":"G. Braun, H. Hoenigschmid, T. Schlager, W. Weber","doi":"10.1109/VLSIC.1999.797250","DOIUrl":"https://doi.org/10.1109/VLSIC.1999.797250","url":null,"abstract":"This paper describes an area penalty free, leakage compensated and noise immune 8F/sup 2/ cell design suitable for high density low power FeRAM generations. The array concept features a 1TIC ferroelectric memory cell containing an additional depletion device (DeFeRAM) controlled by the passing word line in a folded bit line architecture. A highly reliable three level word line driver circuit design is discussed.","PeriodicalId":433264,"journal":{"name":"1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)","volume":"2002 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125768073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
GAD: A 12-GS/s CMOS 4-bit A/D converter for an equalized multi-level link GAD:用于均衡多级链路的12gs /s CMOS 4位A/D转换器
1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326) Pub Date : 1999-06-17 DOI: 10.1109/VLSIC.1999.797232
W. Ellersick, Chih-Kong Ken Yang, Mark Horowitz, William J. Dally
{"title":"GAD: A 12-GS/s CMOS 4-bit A/D converter for an equalized multi-level link","authors":"W. Ellersick, Chih-Kong Ken Yang, Mark Horowitz, William J. Dally","doi":"10.1109/VLSIC.1999.797232","DOIUrl":"https://doi.org/10.1109/VLSIC.1999.797232","url":null,"abstract":"A 4-bit 12-GSample/sec A/D converter (GAD) has been fabricated in a 0.25-/spl mu/m CMOS process to investigate the design of an equalized multi-level link. Clocked differential amplifiers were used to sample the input, followed by high-speed comparators with current-summed offset cancellation. Input bandwidth was measured at 2.5 GHz. Eight 1.5-GSample/sec flash A/D converters were interleaved to achieve the aggregate sample rate.","PeriodicalId":433264,"journal":{"name":"1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127947106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 56
Technical trends of LSI packaging: recent advances in CSPs and high density substrates LSI封装的技术趋势:csp和高密度基板的最新进展
1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326) Pub Date : 1999-06-17 DOI: 10.1109/VLSIC.1999.797239
S. Wakabayashi, M. Shimizu
{"title":"Technical trends of LSI packaging: recent advances in CSPs and high density substrates","authors":"S. Wakabayashi, M. Shimizu","doi":"10.1109/VLSIC.1999.797239","DOIUrl":"https://doi.org/10.1109/VLSIC.1999.797239","url":null,"abstract":"The use of CSPs, Direct Flip Chip Attach and high density substrate should bring tremendous benefits for electronic devices in terms of performance, speed, weight, real estate and cost saving. Several CSPs are already applied for actual mobile electronic devices. Among these CSPs, Super CSP is a newly developed CSP which processed all packaging processes in a wafer form. MOST (Micro Spring On Silicon Technology) is another wafer level packaging technology which has many micro springs on a wafer for board attach. The micro springs were formed by existing wire bonding technology which uses specially designed tool motion. These two CSPs are produced by common rerouting technology with flip chip bumping, i.e. thin film and plating technologies. The structures and manufacturing processes are described and reliability of the CSPs and bumps on wafers are proved as satisfactory for actual application. High density substrates and packages are another important parts for high performance devices and modules. Newly developed high density buildup substrate using polymer coated copper sheets and related technologies such as via filling with copper plating and pre-soldering technology for flip chip attach are described. The reliability of the substrate and flip chip bonding technology are also confirmed.","PeriodicalId":433264,"journal":{"name":"1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131696125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Semiconductor industry evolution for 21/sup st/ century 21世纪半导体产业的演变
1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326) Pub Date : 1999-06-17 DOI: 10.1109/VLSIC.1999.797212
F. Tseng
{"title":"Semiconductor industry evolution for 21/sup st/ century","authors":"F. Tseng","doi":"10.1109/VLSIC.1999.797212","DOIUrl":"https://doi.org/10.1109/VLSIC.1999.797212","url":null,"abstract":"TSMC started the dedicated foundry industry 12 years ago. This not only accelerated the disintegration trend in the semiconductor industry, but also has created a multi-billion dedicated foundry business today. In next decade, foundry paradigm is expected to play an even more important role as foundry companies continue to build their core competency including leading-edge process technologies, advanced and flexible manufacturing capabilities, and customer-oriented service systems. The advent of SOC (system-on-a-chip) and the well entrenchment of the foundry industry will further move the semiconductor industry in the direction of complete disintegration.","PeriodicalId":433264,"journal":{"name":"1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)","volume":"513 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123063602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An 8 b 500 MS/s full Nyquist cascade A/D converter 一个8 b 500ms /s全奈奎斯特级联A/D转换器
1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326) Pub Date : 1999-06-17 DOI: 10.1109/VLSIC.1999.797241
K. Irie, N. Kusayanagi, T. Kawachi, T. Nishibu, Y. Matsumori
{"title":"An 8 b 500 MS/s full Nyquist cascade A/D converter","authors":"K. Irie, N. Kusayanagi, T. Kawachi, T. Nishibu, Y. Matsumori","doi":"10.1109/VLSIC.1999.797241","DOIUrl":"https://doi.org/10.1109/VLSIC.1999.797241","url":null,"abstract":"An 8 b 500 MS/s one-bit-per-stage cascade A/D converter (ADC) has been developed. We achieved 500 MHz one-clock conversion of all the cascade stages with a novel error suppression technique. The measured SNDR is 47 dB (7.6 effective bits) at a 100 kHz input, keeping more than 45 dB (7.2 effective bits) up to the Nyquist frequency. The power dissipation and the active area of the ADC core, including a 1.5 GHz bandwidth sample-and-hold amplifier, are 950 mW from a +2 V/-3.3 V supply and 5.5 mm/sup 2/, respectively.","PeriodicalId":433264,"journal":{"name":"1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133220884","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 10 b, 400 MS/s glitch-free CMOS D/A converter 10b, 400ms /s无故障CMOS D/A转换器
1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326) Pub Date : 1999-06-17 DOI: 10.1109/VLSIC.1999.797240
K. Khanoyan, F. Behbahani, A. Abidi
{"title":"A 10 b, 400 MS/s glitch-free CMOS D/A converter","authors":"K. Khanoyan, F. Behbahani, A. Abidi","doi":"10.1109/VLSIC.1999.797240","DOIUrl":"https://doi.org/10.1109/VLSIC.1999.797240","url":null,"abstract":"Recent reports on high-speed CMOS D/A Converters (DACs) demonstrate clock rates and effective bandwidths of the well-known current-steering DAC architecture of 100's of MHz. In this work, new circuit design and layout methods are applied to a glitch-free 10 b DAC based on the pipelined charge redistribution architecture. Transients in the output current as codes change are called glitches, and because glitch characteristics depend nonlinearly on codes, they result in spurious tones in the output frequency spectrum. In the glitch-free DAC, on the other hand, the analog voltages are sampled and held at each clock cycle. The 0.6 /spl mu/m CMOS prototype described here clocks at up to 400 MS/s, and delivers a superior spurious-free dynamic range (SFDR) over the Nyquist band compared to other CMOS DACs. This circuit is part of a digitally based agile frequency synthesizer for a fast-frequency hopping wireless transmitter, and is intended to drive on-chip capacitor loads.","PeriodicalId":433264,"journal":{"name":"1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130669922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
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