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1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)最新文献

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High-speed cascode sensing scheme for 1.0 V contact-programming mask ROM 高速级联码传感方案1.0 V接触编程掩码ROM
1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326) Pub Date : 1999-06-17 DOI: 10.1109/VLSIC.1999.797248
R. Sasagawa, I. Fukushi, M. Hamaminato, S. Kawashima
{"title":"High-speed cascode sensing scheme for 1.0 V contact-programming mask ROM","authors":"R. Sasagawa, I. Fukushi, M. Hamaminato, S. Kawashima","doi":"10.1109/VLSIC.1999.797248","DOIUrl":"https://doi.org/10.1109/VLSIC.1999.797248","url":null,"abstract":"This paper proposes a high-speed single end sensing scheme. A low-voltage contact-programming mask ROM was designed which utilizes a cascode sense amplifier (S/A). A dummy S/A controls the bit-line pre-charging period to operate the read S/A quickly in spite of high programmed-data-dependence of the bit-line capacitance. The word-line has branches to enhance the cell current with little increase in area. A demonstrated 4 K/spl times/8 bit ROM operates with an access time of 5.7 ns and power of 2.2 mW at 1.0 V, 100 MHz, and 25/spl deg/C.","PeriodicalId":433264,"journal":{"name":"1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)","volume":"66 2-3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123469821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
A 3.6 Gb/s 340 mW 16:1 pipe-lined multiplexer using SOI-CMOS technology 采用SOI-CMOS技术的3.6 Gb/s 340 mW 16:1管道多路复用器
1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326) Pub Date : 1999-06-17 DOI: 10.1109/VLSIC.1999.797224
T. Nakura, K. Ueda, K. Kubo, W. Fernandez, Y. Matsuda, K. Mashiko
{"title":"A 3.6 Gb/s 340 mW 16:1 pipe-lined multiplexer using SOI-CMOS technology","authors":"T. Nakura, K. Ueda, K. Kubo, W. Fernandez, Y. Matsuda, K. Mashiko","doi":"10.1109/VLSIC.1999.797224","DOIUrl":"https://doi.org/10.1109/VLSIC.1999.797224","url":null,"abstract":"This paper describes a 16:1 multiplexer (MUX) using a 0.18 /spl mu/m partially-depleted SOI-CMOS technology. Owing to a selector type architecture with a pipeline structure as well as small junction capacitances of SOI-CMOS devices, the MUX achieves 3.6 Gbps operation dissipating 340 mW at a power supply of 2.0 V.","PeriodicalId":433264,"journal":{"name":"1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132999587","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Compact distributed RLC models for multilevel interconnect networks 多层互连网络的紧凑分布式RLC模型
1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326) Pub Date : 1999-06-14 DOI: 10.1109/VLSIC.1999.797272
J.A. Davis, J. Meindl
{"title":"Compact distributed RLC models for multilevel interconnect networks","authors":"J.A. Davis, J. Meindl","doi":"10.1109/VLSIC.1999.797272","DOIUrl":"https://doi.org/10.1109/VLSIC.1999.797272","url":null,"abstract":"Novel compact expressions that describe the transient response of high-speed resistance, inductance, and capacitance (RLC) coupled transmission lines are rigorously derived for the first time. These new distributed RLC models reveal that peak crosstalk voltage is over 60% larger for 3 GHz and 10 GHz wiring levels than with traditional distributed RC models.","PeriodicalId":433264,"journal":{"name":"1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122631672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Monte Carlo modeling of threshold variation due to dopant fluctuations 由掺杂剂波动引起的阈值变化的蒙特卡罗模型
1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326) Pub Date : 1999-06-14 DOI: 10.1109/VLSIT.1999.799397
D. Frank, Y. Taur, M. Ieong, H.-S.P. Wong
{"title":"Monte Carlo modeling of threshold variation due to dopant fluctuations","authors":"D. Frank, Y. Taur, M. Ieong, H.-S.P. Wong","doi":"10.1109/VLSIT.1999.799397","DOIUrl":"https://doi.org/10.1109/VLSIT.1999.799397","url":null,"abstract":"This paper presents a new, 3-D Monte Carlo approach for modeling random dopant fluctuation effects in MOSFETs. The method takes every silicon atom in the device into account and is generally applicable to arbitrary nonuniform doping profiles. In addition to body dopant fluctuations, the effect of source-drain dopant fluctuations on short-channel threshold voltage is studied for the first time. The result clearly indicates the benefit of retrograde body doping and shallow/abrupt source-drain junctions. It also quantifies the magnitude of threshold voltage variations due to discrete dopant fluctuations in an optimally designed 25 nm MOSFET.","PeriodicalId":433264,"journal":{"name":"1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)","volume":"139 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122058571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 111
Future perspective and scaling down roadmap for RF CMOS RF CMOS的未来展望和缩小路线图
1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326) Pub Date : 1999-06-14 DOI: 10.1109/VLSIT.1999.799394
E. Morifuji, H. Momose, T. Ohguro, T. Yoshitomi, H. Kimijima, F. Matsuoka, M. Kinugawa, Y. Katsumata, H. Iwai
{"title":"Future perspective and scaling down roadmap for RF CMOS","authors":"E. Morifuji, H. Momose, T. Ohguro, T. Yoshitomi, H. Kimijima, F. Matsuoka, M. Kinugawa, Y. Katsumata, H. Iwai","doi":"10.1109/VLSIT.1999.799394","DOIUrl":"https://doi.org/10.1109/VLSIT.1999.799394","url":null,"abstract":"Concept of future scaling-down for RF CMOS has been investigated in terms of fT, fmax, RF noise, linearity, and matching characteristics, based on simulation and experiments. It has been found that gate width and finger length are the key parameters especially in sub-100 nm gate length generations.","PeriodicalId":433264,"journal":{"name":"1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132152020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 32
A 3.3-V 4-Mb nonvolatile ferroelectric RAM with a selectively-driven double-pulsed plate read/write-back scheme 具有选择性驱动双脉冲板读/写回方案的3.3 v 4mb非易失性铁电RAM
1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326) Pub Date : 1900-01-01 DOI: 10.1109/vlsic.1999.797249
Yeonbae Chung, Mun-Kyu Choi, Seung-Kyu Oh, Byung-Gil Jeon, Kang-Deog Suh
{"title":"A 3.3-V 4-Mb nonvolatile ferroelectric RAM with a selectively-driven double-pulsed plate read/write-back scheme","authors":"Yeonbae Chung, Mun-Kyu Choi, Seung-Kyu Oh, Byung-Gil Jeon, Kang-Deog Suh","doi":"10.1109/vlsic.1999.797249","DOIUrl":"https://doi.org/10.1109/vlsic.1999.797249","url":null,"abstract":"Summary form only given. Recently there has been a growing interest in ferroelectric RAM because of its great potential as a future nonvolatile memory. This work presents, for the first time, a 4 Mbit FRAM with novel design techniques: 1) open bitline cell array; 2) selectively-driven double-pulsed plate read/write-back scheme; 3) complementary data preset reference circuitry and relaxation/fatigue/imprint-free reference voltage generator; and 4) unintentional power-off data protection scheme. The prototype device incorporating these circuit schemes shows 75 ns access time, 21 mA active current at 3.3 V, 25/spl deg/C, 110 ns cycle. It measures 116 mm/sup 2/ with 0.6 /spl mu/m CMOS technology.","PeriodicalId":433264,"journal":{"name":"1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129850715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
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