A 3.6 Gb/s 340 mW 16:1 pipe-lined multiplexer using SOI-CMOS technology

Abstract

This paper describes a 16:1 multiplexer (MUX) using a 0.18 /spl mu/m partially-depleted SOI-CMOS technology. Owing to a selector type architecture with a pipeline structure as well as small junction capacitances of SOI-CMOS devices, the MUX achieves 3.6 Gbps operation dissipating 340 mW at a power supply of 2.0 V.