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1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)最新文献

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On-chip active guard band filters to suppress substrate-coupling noise in analog and digital mixed-signal integrated circuits 片上有源保护带滤波器用于抑制模拟和数字混合信号集成电路中的基片耦合噪声
1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326) Pub Date : 1999-06-17 DOI: 10.1109/VLSIC.1999.797235
K. Makie-Fukuda, T. Tsukada
{"title":"On-chip active guard band filters to suppress substrate-coupling noise in analog and digital mixed-signal integrated circuits","authors":"K. Makie-Fukuda, T. Tsukada","doi":"10.1109/VLSIC.1999.797235","DOIUrl":"https://doi.org/10.1109/VLSIC.1999.797235","url":null,"abstract":"An AC coupling configuration of active guard band filters can supply a substrate-coupling-noise cancellation signal to a ground-level substrate by using a single 3 V supply to on-chip circuits. Noise was suppressed to a maximum of less than 0.05 from 100 Hz to 2 MHz in a 0.35 /spl mu/m CMOS test chip. Experiments and a simulation based on the substrate model showed that the noise-suppression effect depends on the guard-band arrangement. The simulation is thus effective for optimizing the arrangement to strongly suppress noise effects.","PeriodicalId":433264,"journal":{"name":"1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134063946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
A pseudo multi-bank DRAM with categorized access sequence 具有分类访问顺序的伪多组DRAM
1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326) Pub Date : 1999-06-17 DOI: 10.1109/VLSIC.1999.797260
S. Shiratake, K. Tsuchida, H. Toda, H. Kuyama, M. Wada, F. Kouno, T. Inaba, H. Akita, K. Isobe
{"title":"A pseudo multi-bank DRAM with categorized access sequence","authors":"S. Shiratake, K. Tsuchida, H. Toda, H. Kuyama, M. Wada, F. Kouno, T. Inaba, H. Akita, K. Isobe","doi":"10.1109/VLSIC.1999.797260","DOIUrl":"https://doi.org/10.1109/VLSIC.1999.797260","url":null,"abstract":"A new architecture which realizes the large bandwidth with virtually the same core circuitry as a conventional DRAM is proposed. The improved row block activation scheme combined with a categorized access sequence improves the bandwidth of the DRAM even with the shared sense amplifier scheme. The data efficiency of the random read/write mixed cycle is improved by the proposed delayed write operation, which fills the write to read command gap effectively. The proposed architecture is successfully examined in the 128 Mbit test vehicle fabricated with a 0.15 /spl mu/m CMOS process.","PeriodicalId":433264,"journal":{"name":"1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122573410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A CMOS imager with new focal-plane motion detectors 带有新型焦平面运动检测器的CMOS成像仪
1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326) Pub Date : 1999-06-17 DOI: 10.1109/VLSIC.1999.797264
F. Okamoto, Y. Fujimoto, T. Nagata, M. Furumiya, K. Hatano, Y. Nakashiba, M. Yotsuyanagi
{"title":"A CMOS imager with new focal-plane motion detectors","authors":"F. Okamoto, Y. Fujimoto, T. Nagata, M. Furumiya, K. Hatano, Y. Nakashiba, M. Yotsuyanagi","doi":"10.1109/VLSIC.1999.797264","DOIUrl":"https://doi.org/10.1109/VLSIC.1999.797264","url":null,"abstract":"A CMOS imager with new focal-plane motion detectors has been developed as the front-end of vision systems. The chip generates both a normal video signal and a local image signal; i.e. the local area where the motion is detected is automatically scanned. Key technologies include a unity-gain two-port pixel, sparsely-placed motion detectors, and a multistage column readout circuit. A 5.8/spl times/8.7 mm/sup 2/ chip fabricated by using 0.35 /spl mu/m CMOS process contains 192/spl times/192 pixels and 7/spl times/7 motion detectors.","PeriodicalId":433264,"journal":{"name":"1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125553774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
CMOS fingerprint sensor with automatic local contrast adjustment and pixel-parallel encoding logic 具有自动局部对比度调整和像素并行编码逻辑的CMOS指纹传感器
1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326) Pub Date : 1999-06-17 DOI: 10.1109/VLSIC.1999.797270
S. Jung, R. Thewes, T. Scheiter, K. Goser, W. Weber
{"title":"CMOS fingerprint sensor with automatic local contrast adjustment and pixel-parallel encoding logic","authors":"S. Jung, R. Thewes, T. Scheiter, K. Goser, W. Weber","doi":"10.1109/VLSIC.1999.797270","DOIUrl":"https://doi.org/10.1109/VLSIC.1999.797270","url":null,"abstract":"A CMOS fingerprint sensor is presented with a self-biasing automatic local contrast adjustment technique for image binarization realized with a passive capacitive network. Pixel-parallel cellular logic is embedded into the sensor array and extracts the characteristic features of the fingerprint image without any additional area consumption. This single-chip sensing and encoding system is suited for low-power and low-cost applications.","PeriodicalId":433264,"journal":{"name":"1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)","volume":"2009 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116847776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A 1 V, 10.4 mW low power DSP core for mobile wireless use 一个1v, 10.4 mW的低功率DSP核心，用于移动无线使用
1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326) Pub Date : 1999-06-17 DOI: 10.1109/VLSIC.1999.797218
T. Shiota, I. Fukushi, R. Ohe, W. Shibamoto, M. Hamaminato, R. Sasagawa, A. Tsuchiya, T. Ishihara, S. Kawashima
{"title":"A 1 V, 10.4 mW low power DSP core for mobile wireless use","authors":"T. Shiota, I. Fukushi, R. Ohe, W. Shibamoto, M. Hamaminato, R. Sasagawa, A. Tsuchiya, T. Ishihara, S. Kawashima","doi":"10.1109/VLSIC.1999.797218","DOIUrl":"https://doi.org/10.1109/VLSIC.1999.797218","url":null,"abstract":"We designed a 1 V, 50 MHz, 16-bit DSP core using a 0.25-/spl mu/m Dual Vt Library, SRAM, and Mask ROM tailored for 1 V operation. The core architecture was enhanced using an alternate MAC to recover slower circuitry. A 1.0 V to 1.5 V voltage up converter with 59% power efficiency and a 450 ps 1 V to 2.5 V level converter were implemented. A power simulation with a CODEC firmware showed 10.4 mW, about a quarter of a standard DSP.","PeriodicalId":433264,"journal":{"name":"1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121937547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A sampling weak-program method to tighten Vth-distribution of 0.5 V for low-voltage flash memories 一种收紧0.5 V电压分布的采样弱程序方法
1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326) Pub Date : 1999-06-17 DOI: 10.1109/VLSIC.1999.797226
H. Shiga, T. Tanzawa, A. Umezawa, T. Taura, T. Miyaba, M. Saito, S. Kitamura, S. Mori, S. Atsumi
{"title":"A sampling weak-program method to tighten Vth-distribution of 0.5 V for low-voltage flash memories","authors":"H. Shiga, T. Tanzawa, A. Umezawa, T. Taura, T. Miyaba, M. Saito, S. Kitamura, S. Mori, S. Atsumi","doi":"10.1109/VLSIC.1999.797226","DOIUrl":"https://doi.org/10.1109/VLSIC.1999.797226","url":null,"abstract":"Recently, it has become increasingly important to lower the supply voltage of fast access time NOR flash EEPROMs for a low power handheld digital equipment. In order to scale the boosted word-line voltage for reading memory data with low power supply, it is necessary to tighten the erased-Vth distribution. The self-convergence method has been proposed to tighten the Vth-distribution within 2 V. However, it's not available to tighten the width below 1 V due to the high power consumption and long converging time. Therefore, the bit-by-bit weak program after over-erase-verify is needed. This paper shows a problem of the bit-by-bit weak program and proposes a sampling method of weak program for a solution, which can achieve 0.5 V in the Vth-distribution width, resulting in lowering the word-line voltage for less than 1.5 V operation.","PeriodicalId":433264,"journal":{"name":"1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131795543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
CMOS 10 MHz-IF downconverter with on-chip broadband circuit for large image-suppression 带有片上宽带电路的CMOS 10mhz - if下变频器用于大图像抑制
1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326) Pub Date : 1999-06-17 DOI: 10.1109/VLSIC.1999.797244
F. Behbahani, Y. Kishigami, J. Leete, A. Abidi
{"title":"CMOS 10 MHz-IF downconverter with on-chip broadband circuit for large image-suppression","authors":"F. Behbahani, Y. Kishigami, J. Leete, A. Abidi","doi":"10.1109/VLSIC.1999.797244","DOIUrl":"https://doi.org/10.1109/VLSIC.1999.797244","url":null,"abstract":"A highly selective superheterodyne radio receiver has so far defied complete integration because it is difficult to adequately reject the image with only on-chip circuits. Practical quadrature downconversion mixers, limited by gain mismatch and phase inaccuracy, usually reject the image by no more than 35 dB or so. This may be good enough in a low intermediate frequency (IF) receiver for certain cellular systems such as GSM or DECT, because the base station limits the relative power of the adjacent channels comprising the image. However, in non-cellular or unregulated ISM bands the adjacent channel level, and therefore the strength of the image, is relatively unconstrained. This paper describes a circuit that rejects the image by almost 60 dB over two octaves of frequency centered at 10 MHz with no need for adjustment or tuning. It is intended for use in a fully integrated low-IF superheterodyne receiver. The prototype circuit is implemented in 0.6 /spl mu/m CMOS.","PeriodicalId":433264,"journal":{"name":"1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134622162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
CMOS technology: Present and future CMOS技术:现在与未来
1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326) Pub Date : 1999-06-17 DOI: 10.1109/VLSIC.1999.797216
B. Davari
{"title":"CMOS technology: Present and future","authors":"B. Davari","doi":"10.1109/VLSIC.1999.797216","DOIUrl":"https://doi.org/10.1109/VLSIC.1999.797216","url":null,"abstract":"Presently, we are going through an exciting phase of the semiconductor industry, as the miniaturization of the dimensions is accelerated and at the same time some of the fundamental limits of device scaling, as well as optical lithography, are rapidly drawing near. In this paper, the impact of these limits on the future development of CMOS technology are examined and some of the advanced device, interconnect, and functional integration techniques to further extend technology scaling are discussed. Beyond these advances, the spectacular success that the semiconductor industry has had can only continue by increasing the silicon chip functional integration, once the device performance and miniaturization starts to saturate. The success of this phase of the semiconductor business relies heavily on circuit and architectural innovations, aided by embedded technologies. The cost of the integrated system on a chip should remain significantly below the price of the system that it intends to replace in addition to delivering added performance.","PeriodicalId":433264,"journal":{"name":"1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114470830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
A compact 54/spl times/54-bit multiplier with improved Wallace-tree structure 一个紧凑的54/spl倍/54位乘法器与改进的华莱士树结构
1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326) Pub Date : 1999-06-17 DOI: 10.1109/VLSIC.1999.797219
N. Itoh, Y. Naemura, H. Makino, Y. Nakase
{"title":"A compact 54/spl times/54-bit multiplier with improved Wallace-tree structure","authors":"N. Itoh, Y. Naemura, H. Makino, Y. Nakase","doi":"10.1109/VLSIC.1999.797219","DOIUrl":"https://doi.org/10.1109/VLSIC.1999.797219","url":null,"abstract":"As multimedia applications become popular, computers increasingly require high-speed floating point (FP) processing for three-dimension computer graphics (3DCG). Among various FP constructions, the FP multiplication is critical in both speed and area. The high-speed multiplier (MPY) frequently adopts the Wallace-tree method. However, this method requires complicated layout which increases the design cost and the chip area. We propose the new construction method of Wallace-tree which reduces the area with a simple layout. This paper describes a new method and its application to a 54/spl times/54-bit MPY design.","PeriodicalId":433264,"journal":{"name":"1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131762172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A high-resolution capacitive fingerprint sensing scheme with charge-transfer technique and automatic contrast emphasis 一种基于电荷转移和自动对比度的高分辨率电容式指纹传感方案
1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326) Pub Date : 1999-06-17 DOI: 10.1109/VLSIC.1999.797269
H. Morimura, S. Shigematsu, K. Machida
{"title":"A high-resolution capacitive fingerprint sensing scheme with charge-transfer technique and automatic contrast emphasis","authors":"H. Morimura, S. Shigematsu, K. Machida","doi":"10.1109/VLSIC.1999.797269","DOIUrl":"https://doi.org/10.1109/VLSIC.1999.797269","url":null,"abstract":"A novel capacitive fingerprint sensing scheme obtains an accurate fingerprint image through direct finger surface contact with a pixel array that includes sensor cells. A sensing circuit with a differential charge-transfer amplifier suppresses the influence of the parasitic capacitance. For high-resolution A/D conversion, the output dynamic range is widened by transforming the sensed voltage to a time axis. Moreover, the sensing circuit includes an automatic contrast emphasis scheme. The characteristics were evaluated by a test chip using the 0.5-/spl mu/m CMOS process, and a single-chip fingerprint sensor/identifier LSI using this scheme is demonstrated.","PeriodicalId":433264,"journal":{"name":"1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)","volume":"335 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132405271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
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