一个1v, 10.4 mW的低功率DSP核心，用于移动无线使用

1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326) Pub Date : 1999-06-17 DOI:10.1109/VLSIC.1999.797218

T. Shiota, I. Fukushi, R. Ohe, W. Shibamoto, M. Hamaminato, R. Sasagawa, A. Tsuchiya, T. Ishihara, S. Kawashima

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引用次数: 5

摘要

我们设计了一个1 V, 50 MHz, 16位DSP核心，使用0.25-/spl mu/m双Vt库，SRAM和为1 V操作量身定制的掩模ROM。使用备用MAC来恢复较慢的电路，增强了核心架构。实现了一个1.0 V至1.5 V电压上升转换器，功率效率为59%，以及一个450 ps的1 V至2.5 V电平转换器。CODEC固件的功率模拟显示为10.4 mW，约为标准DSP的四分之一。

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A 1 V, 10.4 mW low power DSP core for mobile wireless use

We designed a 1 V, 50 MHz, 16-bit DSP core using a 0.25-/spl mu/m Dual Vt Library, SRAM, and Mask ROM tailored for 1 V operation. The core architecture was enhanced using an alternate MAC to recover slower circuitry. A 1.0 V to 1.5 V voltage up converter with 59% power efficiency and a 450 ps 1 V to 2.5 V level converter were implemented. A power simulation with a CODEC firmware showed 10.4 mW, about a quarter of a standard DSP.

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1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)

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