H. Shiga, T. Tanzawa, A. Umezawa, T. Taura, T. Miyaba, M. Saito, S. Kitamura, S. Mori, S. Atsumi
{"title":"A sampling weak-program method to tighten Vth-distribution of 0.5 V for low-voltage flash memories","authors":"H. Shiga, T. Tanzawa, A. Umezawa, T. Taura, T. Miyaba, M. Saito, S. Kitamura, S. Mori, S. Atsumi","doi":"10.1109/VLSIC.1999.797226","DOIUrl":null,"url":null,"abstract":"Recently, it has become increasingly important to lower the supply voltage of fast access time NOR flash EEPROMs for a low power handheld digital equipment. In order to scale the boosted word-line voltage for reading memory data with low power supply, it is necessary to tighten the erased-Vth distribution. The self-convergence method has been proposed to tighten the Vth-distribution within 2 V. However, it's not available to tighten the width below 1 V due to the high power consumption and long converging time. Therefore, the bit-by-bit weak program after over-erase-verify is needed. This paper shows a problem of the bit-by-bit weak program and proposes a sampling method of weak program for a solution, which can achieve 0.5 V in the Vth-distribution width, resulting in lowering the word-line voltage for less than 1.5 V operation.","PeriodicalId":433264,"journal":{"name":"1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.1999.797226","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
Recently, it has become increasingly important to lower the supply voltage of fast access time NOR flash EEPROMs for a low power handheld digital equipment. In order to scale the boosted word-line voltage for reading memory data with low power supply, it is necessary to tighten the erased-Vth distribution. The self-convergence method has been proposed to tighten the Vth-distribution within 2 V. However, it's not available to tighten the width below 1 V due to the high power consumption and long converging time. Therefore, the bit-by-bit weak program after over-erase-verify is needed. This paper shows a problem of the bit-by-bit weak program and proposes a sampling method of weak program for a solution, which can achieve 0.5 V in the Vth-distribution width, resulting in lowering the word-line voltage for less than 1.5 V operation.