{"title":"一个紧凑的54/spl倍/54位乘法器与改进的华莱士树结构","authors":"N. Itoh, Y. Naemura, H. Makino, Y. Nakase","doi":"10.1109/VLSIC.1999.797219","DOIUrl":null,"url":null,"abstract":"As multimedia applications become popular, computers increasingly require high-speed floating point (FP) processing for three-dimension computer graphics (3DCG). Among various FP constructions, the FP multiplication is critical in both speed and area. The high-speed multiplier (MPY) frequently adopts the Wallace-tree method. However, this method requires complicated layout which increases the design cost and the chip area. We propose the new construction method of Wallace-tree which reduces the area with a simple layout. This paper describes a new method and its application to a 54/spl times/54-bit MPY design.","PeriodicalId":433264,"journal":{"name":"1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A compact 54/spl times/54-bit multiplier with improved Wallace-tree structure\",\"authors\":\"N. Itoh, Y. Naemura, H. Makino, Y. Nakase\",\"doi\":\"10.1109/VLSIC.1999.797219\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"As multimedia applications become popular, computers increasingly require high-speed floating point (FP) processing for three-dimension computer graphics (3DCG). Among various FP constructions, the FP multiplication is critical in both speed and area. The high-speed multiplier (MPY) frequently adopts the Wallace-tree method. However, this method requires complicated layout which increases the design cost and the chip area. We propose the new construction method of Wallace-tree which reduces the area with a simple layout. This paper describes a new method and its application to a 54/spl times/54-bit MPY design.\",\"PeriodicalId\":433264,\"journal\":{\"name\":\"1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)\",\"volume\":\"6 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-06-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.1999.797219\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.1999.797219","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A compact 54/spl times/54-bit multiplier with improved Wallace-tree structure
As multimedia applications become popular, computers increasingly require high-speed floating point (FP) processing for three-dimension computer graphics (3DCG). Among various FP constructions, the FP multiplication is critical in both speed and area. The high-speed multiplier (MPY) frequently adopts the Wallace-tree method. However, this method requires complicated layout which increases the design cost and the chip area. We propose the new construction method of Wallace-tree which reduces the area with a simple layout. This paper describes a new method and its application to a 54/spl times/54-bit MPY design.
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